26 results about "Pull in voltage" patented technology

The invention relates to an I2C interface circuit, a corresponding electronic device and an operation method. A first comparator stage of the I2C interface circuit compares a received clock signal to a low threshold and a high threshold to generate a clock signal. A second comparator stage of the I2C interface circuit compares the received data signal to a low threshold and a high threshold to generate the data signal. The first comparator stage and the second comparator stage are default programmed to be in a first mode of operation in which the low threshold is a first score of the high pull-up voltage and the high threshold is a second score of the low pull-up voltage. In response to a received programming frame identifying a current pull-up voltage value, the first comparator stage and the second comparator stage are switchable to a second mode of operation in which the low threshold is a first score of the current pull-up voltage value and the high threshold is a second score of the current pull-up voltage value.

Embodiments of the present application relate to the technical field of semiconductors, and provide an I / O driver and an electronic device, used for improving the performance of an I / O driver. The I / O driver comprises a pull-up circuit, a pull-down circuit and an input / output end. The pull-up circuit is coupled between a power supply voltage end and the input / output end and is used for generating a pull-up voltage on the basis of a first control signal. The pull-down circuit is coupled between a reference ground voltage end and the input / output end and is used for generating a pull-down voltage on the basis of a second control signal. The input / output end is used for outputting the pull-up voltage and the pull-down voltage. A transistor in the pull-up circuit and / or the pull-down circuit is a three-dimensional field effect transistor. A two-dimensional field effect transistor is replaced with the three-dimensional field effect transistor, improving the performance of the I / O driver, and reducing the area of the I / O driver.

The application discloses a small terahertz MEMS single-pole four-throw switch based on a shared composite beam and belongs to the technical field of radio frequency MEMS. The single-pole four-throw switch based on the whole beam is composed of a microstrip main feeder, a bifurcated transition structure, a low-loss switch structure and a microstrip output line. The MEMS switch is formed into a high-isolation symmetric structure by a metal-dielectric whole composite beam, and the switch has a minimum size and a low pull-down voltage by combining a crane-shaped arm and a shared folding arm. The corresponding part of the beam is pulled down by electrostatic force generated by the potential difference between the bottom electrode and the shared beam metal part, and the metal contact on the beam makes the corresponding microstrip output line conductive. When one of the MEMS switch lines is turned on and the other lines are turned off, the signal transmission is completed. The reconfigurable switch is formed by four asymmetric single-pole single-throw switch units through symmetric and compact arrangement, has high isolation in an ultra-wide frequency band, has a channel reflection coefficient less than -15 dB in a DC-350 GHz frequency band, has an in-band insertion loss less than 1.8 dB, and has an isolation greater than 15 dB.

A multi-purpose programmable input / output (I / O) circuit is disclosed. The programmable I / O circuit includes a microcontroller and an interface circuit communicatively coupled to each other. The interface circuit comprises an input circuit, a pull-up circuit, a pull-down circuit and a measurement circuit. The microcontroller is configured to generate a first input signal and a second input signal provided to the input, and is further configured to receive a measurement signal on a measurement input. In response to a setting of the first input signal, the input circuit activates the pull-up circuit to generate a pull-up voltage on the output pin of the interface circuit. In response to a setting of the second input signal, the input circuit activates the pull-down circuit to generate a pull-down voltage on the output pin. The microcontroller may also measure a value of an electrical parameter (e.g., current or voltage) based on a measurement signal received from the measurement circuit.

A voltage generating circuit includes: an analog voltage generating circuit having a first amplifier therein, which is configured to generate an output voltage in response to a first reference voltage and a feedback voltage, and first and second digital driving circuits. The first digital driving circuit is configured to selectively provide a pull-up voltage boost to the output voltage generated by the first amplifier, in response to comparing the feedback voltage to a second reference voltage having a magnitude less than the first reference voltage by a first offset voltage. The second digital driving circuit is configured to selectively provide a pull-down voltage boost to the output voltage generated by the first amplifier, in response to comparing the feedback voltage to a third reference voltage having a magnitude greater than the first reference voltage by a second offset voltage.

The invention relates to a door lock (1) for locking a door (3) of a motor vehicle (2), comprising a diagnosable switch (4) comprising a parallel resistor (6), a switch (7) configured to determine the position of the door (3), and a series resistor (8), the parallel resistor (6) being connected in parallel with the switch (7) and connected in series with the series resistor (8), and a diagnostic circuit (5) for detecting the position of the door (3), comprising a series resistor (8), a pull-up resistor (11) configured to receive a pull-up voltage from a power source (16), a voltage divider (12) comprising a midpoint (13), and a microcontroller (14), where the diode (10) is connected between the series resistor (8) and the voltage divider (12), the midpoint (13) is connected to the microcontroller (14), the diode (10) is connected to the pull-up resistor (11) towards an anode of the voltage divider (12), and the diode (10) is connected to the microcontroller (14) towards a cathode of the voltage divider (12). And the microcontroller (14) is configured to determine whether the midpoint voltage of the midpoint (13) is related to the switching position of the switch (7).

The embodiment of the invention provides an I / O driver and electronic equipment, relates to the technical field of semiconductors, and is used for improving the performance of the I / O driver. The I / O driver comprises a pull-up circuit, a pull-down circuit and an input / output end. The pull-up circuit is coupled between a power supply voltage end and an input / output end and is used for generating a pull-up voltage according to a first control signal. The pull-down circuit is coupled between the reference ground voltage end and the input / output end and is used for generating pull-down voltage according to the second control signal. The input / output end is used for outputting pull-up voltage and pull-down voltage. Wherein the transistors in the pull-up circuit and / or the pull-down circuit are three-dimensional field effect transistors. By replacing a two-dimensional field effect transistor with a three-dimensional field effect transistor, the performance of the I / O driver can be improved, and the area of the I / O driver can be reduced.

The invention discloses a transmitter and a ringing suppression circuit and method. The transmitter includes a positive differential terminal and a negative differential terminal. The ringing suppression circuit comprises a bias current module used for generating bias current; the pull-down module is used for generating pull-down voltage corresponding to common-mode voltage according to the bias current; the pull-up module is used for generating pull-up voltage corresponding to common-mode voltage according to the bias current, and when the transmitter jumps from the dominant state to the implicit state, the ringing suppression circuit clamps the positive differential terminal and the negative differential terminal to the common-mode voltage. The ringing suppression circuit generates a driving current for ringing suppression according to a bias current to improve a current driving capability, and dynamically enables a ringing suppression function according to a signal state change to reduce static power consumption.

An inverter (500), logic circuit, word line circuit, memory and integrated system, wherein the inverter (500) mainly comprises an inverting circuit (501) and an adjusting circuit (502-1). The inverting circuit (501) is used for inverting an input signal, and the adjusting circuit (502-1) is used for providing a smaller pull-up voltage for the inverting circuit (501) in standby mode and a larger pull-up voltage for the inverting circuit (501) in working mode according to a control signal. The adjusting circuit (502-1) provides the smaller pull-up voltage in standby mode, thereby reducing the leakage current of the inverter (500) in standby mode, and also reducing the influence on the working performance of the inverting circuit (501) in working mode of the inverter (500), so that the inverter (500) can work normally.

Embodiments of the present application provide a resistance measurement circuit, a resistance measurement method, an electronic device and a resistance measurement device. The resistance measurement method is applied to the resistance measurement circuit, and the resistance measurement method comprises: acquiring a pull-up voltage output by a voltage generator to a voltage division detection circuit; determining a reference array resistance value of a reference resistance array based on an adjustable resistance range of the reference resistance array, and controlling the opening and closing states of all switches to make the current resistance value of the reference resistance array reach the reference array resistance value; acquiring a node voltage corresponding to a connection node between the reference resistance array and a to-be-measured resistance; and determining a target resistance value of the to-be-measured resistance based on the pull-up voltage, the node voltage and the reference array resistance value of the reference resistance array. The method controls the low-cost resistance measurement circuit to achieve efficient and accurate resistance value measurement of the to-be-measured resistance.

The utility model relates to the technical field of circuits, in particular to a constant-current electromagnetic coil driving circuit structure, which is characterized by comprising an input control signal, a first circuit module, a second circuit module, a third circuit module and a pull-up voltage source which are connected in sequence, the second circuit module comprises a PWM comparator, a first hysteresis resistor, a hysteresis reference voltage source, a hysteresis comparator, a current-limiting resistor and an N-MOS which are connected in sequence, the PWM comparator is connected with the first circuit module, the N-MOS and the third circuit module form a constant current circuit through the PWM comparator and the hysteresis comparator, and the PWM comparator is connected with the first hysteresis resistor. A hardware constant-current circuit is formed by a comparator, the defect that the suction force of a PWM driving electromagnetic coil is reduced along with the increase of the temperature is overcome, and continuous and stable electromagnetic suction force is ensured.

Disclosed is a delay timer, the delay timer of the embodiment of the application has a series structure of a current source and a capacitor, and a control circuit changes the topological relation of the capacitor in the circuit according to the state (high level or low level) of an input signal, so that the charging and discharging of the capacitor voltage can be counted after the input signal jumps, and at the same time, the ground end of an inverting circuit used as a buffer circuit is connected to one end of the capacitor instead of a reference ground, so that the pull-up voltage (power supply voltage) can be introduced to affect the delay time of the delay timer, thereby reducing the negative influence of the fluctuation of the threshold voltage inherent in the inverting circuit on the accuracy of the delay time of the delay timer. The circuit structure of the delay timer of the embodiment of the application is simple, the number of components is small, and the delay precision is high.

A multi-programmable input / output (I / O) circuit is disclosed. A programmable I / O circuit includes a microcontroller and an interface circuit communicatively coupled to one another. The interface circuit includes an input circuit, a pull-up circuit, a pull-down circuit, and a measurement circuit. The microcontroller is configured to generate first and second input signals that are provided to the input, and further configured to receive, on a measurement input, the measurement signal. In response to assertion of the first input signal, the input circuit activates the pull-up circuit to generate a pull-up voltage on an output pin of the interface circuit. In response to assertion of the second input signal, the input circuit activates the pull-down circuit to generate a pull-down voltage on the output pin. The microcontroller may also measure the value of an electrical parameter (e.g., a current or a voltage) based on the measurement signal received from the measurement circuit.

A semiconductor device includes a pull-up source voltage generation circuit configured to drive a pull-up voltage to a normal voltage during a normal period and to drive the pull-source voltage to a test voltage during a test period. The semiconductor device also includes a pull-down source voltage generation circuit configured to drive a pull-down voltage to a ground voltage during the normal period and to drive the pull-down source voltage to a bit line pre-charge voltage during the test period. The semiconductor device further includes an equalization control signal driver configured to receive the pull-up source voltage and the pull-down source voltage to drive an equalization control signal for equalizing voltage levels of an internal bit line pair of a bit line sense amplifier.

The invention relates to the technical field of electronic circuit diagnosis, and discloses a pre-operation diagnosis circuit and method for a high-drive load, the circuit comprises a pull-up voltage source, an electronic controller and a high-drive chip, and an enabling pin of the electronic controller is connected with a controlled end of an active switch; the electronic controller is used for outputting a square wave pulse signal to the active switch through the enabling pin, receiving a feedback voltage signal through the first input pin, and judging whether the high-drive load has a short power supply fault or an open circuit fault by combining whether the feedback voltage signal is fully deviated when the square wave pulse signal is at a high level and a low level; whether a short power supply fault or an open-circuit fault exists or not can be judged before the high-drive load operates, and diagnosis before operation is achieved.

Semiconductor memory device (200, 400, 700) comprising: a matrix (202, 800) of memory cells (204, 302, 804, 814, 816) arranged in a plurality of rows and columns (300), each memory cell (204, 302, 814, 816) having a plurality of bit cell transistors (308); and a plurality (802) of write assist circuits (100, 206, 208, 510, 808) comprising one or more write assist circuits (100, 206, 208, 510, 808) in each column (300) of the matrix (202, 800) of memory cells (204, 302, 804, 814, 816), wherein each write assist circuit (100, 206, 208, 808) is configured to provide a core voltage (VDDAI, 112, 210) for memory cells (204, 302, 804, 814, 816) in the same column (300) and to lower the core voltage (VDDAI, 112, 210) during a write operation, and wherein the one or more Write assistant circuits (100, 206, 208, 510, 808) comprising: a first pair of transistors (102, 104) connected between a pull-up voltage (VDD, 110) and a core voltage bus (VDDAI, 112, 210), the first pair of transistors (102, 104) being configured to connect the core voltage bus (VDDAI, 112, 210) to the pull-up voltage (VDD, 110) during the write operation; and a second pair of transistors (106, 108) connected between a pull-down voltage (VSS, 116) and the core voltage bus (VDDAI, 112, 210), the second pair of transistors (106, 108) each having a gate terminal receiving an enable signal (LCV_Enb, 118, 214, 518) that causes the second pair of transistors (106, 108) to connect the core voltage bus (VDDAI, 112, 210) to the pull-down voltage (VSS, 116) during the write operation;wherein the matrix (202, 800) of memory cells (204, 302, 804, 814, 816) and the plurality (802) of write assist circuits (100, 206, 208, 510, 808) have a common semiconductor layout (400, 700) having a repeating structure of gate regions and active regions, wherein each of the plurality (802) of write assist circuits (100, 206, 208, 510, 808) uses a layout area (808) of the common semiconductor layout (400, 700) that corresponds to an area for three adjacent memory cells (204, 302, 804, 814, 816) in a column (300) of the matrix (202, 800) of memory cells (204, 302, 804, 814, 816) corresponds.;

The present invention provides a chip testing method, device and circuit. The chip testing method includes: in response to a first type of preset test instruction, controlling a grounding pin of a chip under test to connect to a non-zero potential, where the first type of preset control instruction at least includes an ODT detection instruction; outputting a control stream corresponding to the preset control instruction to the chip under test, detecting a parameter corresponding to the preset test instruction of the chip under test and outputting a detection result. Embodiments of the present invention can perform ODT testing of a chip without externally connecting a pull-up voltage.

The utility model relates to the field of charging piles, in particular to a gun insertion detection circuit based on a direct-current charging pile, and the circuit comprises an input end PD1ADC which is used for receiving a signal transmitted by an electric vehicle; the input end of the isolation circuit is coupled to the input end PD1ADC, and the isolation circuit isolates signals received by the input end PD1ADC; the input end of the amplifying circuit is coupled to the output end of the isolating circuit, and the amplifying circuit amplifies the signal output by the isolating circuit and then outputs the amplified signal; the output end ADCPD1 is used for outputting the signal amplified by the amplifying circuit; the pull-up circuit is coupled between the input end PD1ADC and the input end of the isolation circuit and is used for pulling up voltage; and the pull-down circuit is coupled between the input end PD1ADC and the input end of the isolation circuit and pulls down voltage. The method has the effects of reducing the design cost and improving the adaptability.

The application discloses a self-adaptive pre-pull-down circuit and method applied to a synchronous rectification driving chip, samples a gate voltage VG of a synchronous rectification tube and obtains a pre-pulled comparison threshold voltage VFB by voltage reduction; samples a drain-source voltage VD of the synchronous rectification tube and compares the voltage VD with the voltage VFB, if the voltage VD is less than the voltage VFB, outputs a control signal to a VG voltage driving unit of the chip, reduces the voltage VG until the VG is pulled down to the ground when a turn-off threshold is reached. Because the voltage VG has been pulled down in advance, the voltage VG cannot be pulled back to a low value, so the voltage VG can be quickly pulled down to the ground. The application adjusts the gate potential of the synchronous rectification tube by adding the pre-pull-down circuit, thereby prolonging the conduction time of the synchronous rectification tube, reducing the conduction time of a body diode and improving the efficiency of the synchronous rectification.

A first comparator stage of an I2C interface circuit compares a received clock signal to low and high thresholds to produce a clock signal. A second comparator stage of the I2C interface circuit compares a received data signal to the low and high thresholds to produce a data signal. The first and second comparator stages are programmed by default in a first operating mode where the low threshold is a first fractional value of the high pull-up voltage and the high threshold is a second fractional value of the low pull-up voltage. The first and second comparator stages are switchable, in response to a received programming frame identifying a current pull-up voltage value, to a second operating mode where the low threshold is the first fractional value of the current pull-up voltage value and the high threshold is the second fractional value of the current pull-up voltage value.

A memory device includes a sense amplifying circuit coupled between a pull-up voltage line and a pull-down voltage line and configured to sense and amplify data of bit lines according to a sensing control signal; a fail detection circuit configured to calculate counting values of fail bits for each temperature based on the data and configured to generate a minimum error code for each temperature by detecting a minimum value for each temperature from the counting values for each temperature, in response to a test mode signal; and a sense amplifying control circuit configured to drive the pull-up voltage line and the pull-down voltage line by generating a pull-up voltage and a pull-down voltage corresponding to current temperature information based on the minimum error code for each temperature and configured to generate the sensing control signal according to the test mode signal.

The invention discloses a display panel and a pixel driving circuit and a driving method thereof. The pixel driving circuit is used for driving a pixel unit to emit light and comprises a pulse width modulation module and a pulse amplitude modulation module. The pulse amplitude modulation module comprises a driving transistor which is connected in series with the pixel unit between a working voltage and a ground voltage; the gate of the driving transistor is used for inputting a first data signal; and the first compensation unit is connected with the driving transistor and is used for automatically compensating the threshold drift of the driving transistor. The pulse width modulation module comprises a pull-down transistor, the drain of which is connected to the gate of the driving transistor, the source of which is connected to a pull-down voltage, and the gate of which is used for inputting a second data signal; and the second compensation unit is connected with the pull-down transistor and is used for automatically compensating the threshold drift of the pull-down transistor. According to the display panel and the pixel driving circuit and driving method thereof, the threshold voltage is dynamically compensated, so that the influence caused by threshold drift can be eliminated.

The invention discloses a load-end Type-C interface water vapor detection circuit and detection method. The circuit comprises the steps that a pull-up module drives a detection module to sample a configuration channel of an interface; a pull-up resistor in the pull-up module is connected with the configuration channel through a switch S1, and a pull-down resistor is connected with the configuration channel through a switch S2; the detection module compares the upper threshold voltage Vth with the input voltage Vin and compares the lower threshold voltage Vtl with the input voltage Vin, the delayer Y1 compares the change condition of the input voltage Vin, and the counter outputs the counting result of the number of clocks. Therefore, only one pull-up voltage is introduced, other circuit designs are integrated in the power management chip, the Type-C interface does not need to be subjected to design change, water vapor intrusion can be quantitatively detected by analyzing detection modes such as rise time, a rise and fall curve and partial voltage value change of the input voltage, the upgrading and refitting cost is low, the use of the existing interface is not influenced, and the application range is wide. The application scene is wide.

A shift register unit is provided, comprising a shift register circuit, wherein the shift register circuit comprises a display input circuit, at least two driver output circuits capable of outputting display driver pulses sequentially, each of the driver output circuits being configured to write a signal provided by the driver clock signal input terminal to a driver signal output terminal in response to the control of an active level signal at a pull-up node;wherein the shift register circuit further comprises a first pull-up voltage stabilization circuit and / or a second pull-up voltage stabilization circuit, wherein the first pull-up voltage stabilization circuit is connected to the pull-up node and is configured at least to keep the voltage at the pull-up node unchanged during the time in which the first driver output circuit outputs a display driver pulse, and wherein the second pull-up voltage stabilization circuit is connected to the pull-up node and is configured at least to keep the voltage at the pull-up node unchanged during the time in which the last driver output circuit outputs a display driver pulse.

A pull-up voltage detection circuit is for use in a serial bus. The serial bus includes a communication signal. During a communication interval, the communication signal is toggled based on a pull-up voltage for communicating on the serial bus via open-drain scheme. The pull-up voltage detection circuit includes: at least one comparator circuit for comparing the communication signal or a divided voltage thereof with at least one reference voltage in a detection procedure, so as to generate at least one comparison result; and a selector circuit for selecting one of plural predetermined voltages according to the at least one comparison result. The selected predetermined voltage serves as a logic threshold voltage corresponding to the pull-up voltage. In the communication interval, the logic state of the communication signal is determined by comparing the communication signal and the logic threshold voltage for communicating on the serial bus.

A semiconductor device includes a pull-up source voltage generation circuit configured to drive a pull-up voltage to a normal voltage during a normal period and to drive the pull-source voltage to a test voltage during a test period. The semiconductor device also includes a pull-down source voltage generation circuit configured to drive a pull-down voltage to a ground voltage during the normal period and to drive the pull-down source voltage to a bit line pre-charge voltage during the test period. The semiconductor device further includes an equalization control signal driver configured to receive the pull-up source voltage and the pull-down source voltage to drive an equalization control signal for equalizing voltage levels of an internal bit line pair of a bit line sense amplifier.