Liquid crystal panel and active matrix substrate used therefor
A liquid crystal panel and active matrix technology, applied in the field of liquid crystal panels and active matrix substrates, can solve the problem of high pixel aperture ratio and achieve the effect of suppressing flickering
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Embodiment approach 1
[0067] Figure 5 (a) and (b) are a cross-sectional view and a plan view showing a region corresponding to one pixel of the TFT substrate 10A included in the liquid crystal panel of the first embodiment.
[0068] Such as Figure 5 As shown in (a) and (b), the TFT substrate 10A has a gate wiring 2 extending in the horizontal direction provided on the transparent insulating substrate 11, and a gate wiring 2 is provided in a direction (typically a vertical direction) crossing the gate wiring 2. The extended source wiring 4 and the TFT 5 connecting the gate wiring 2 and the source wiring 4 have a structure.
[0069] The TFT 5 includes: a gate electrode 12 connected to the gate wiring 2; a gate insulating layer 20 covering the gate electrode 12; and the source electrode 14 and the drain electrode 15 electrically connected to the oxide semiconductor layer 16 . Source electrode 14 is connected to source wiring 4 . In addition, source electrode 14 and drain electrode 15 are arrange...
Embodiment approach 2
[0080] Figure 6 (a) and (b) are a cross-sectional view and a plan view showing a region corresponding to one pixel of the TFT substrate 10B included in the liquid crystal panel of the second embodiment. In addition, for simplicity of description, the same reference numerals are attached to the same components as those in Embodiment 1, and description thereof will be omitted.
[0081] In the TFT substrate 10B of the present embodiment, pixels are configured such that the feed-through voltage ΔVd1 of the peripheral pixel P1 is smaller than the feed-through voltage ΔVd2 of the central pixel P2 . More specifically, the channel width (the width of the drain electrode 15) of the TFT 5 is designed to be smaller at the peripheral portion of the panel so that Figure 6 In the region C2 surrounded by the dotted line in (b), the parasitic capacitance Cgd between the gate and the drain of the peripheral pixel P1 is smaller than the parasitic capacitance Cgd between the gate and the drai...
Embodiment approach 3
[0086] Figure 7 (a) and (b) are a cross-sectional view and a plan view showing a region corresponding to one pixel of the TFT substrate 10C included in the liquid crystal panel of the third embodiment. In addition, for the sake of simplicity of description, the same reference numerals are assigned to the same components as those in Embodiments 1 and 2, and description thereof will be omitted.
[0087] In the TFT substrate 10C of the present embodiment, pixels are configured such that the feed-through voltage ΔVd1 of the peripheral pixel P1 is smaller than the feed-through voltage ΔVd2 of the central pixel P2 . More specifically, in Figure 7 In a region C3 surrounded by a dotted line in (a), the storage capacitor Cs of the peripheral pixel P1 is set to be larger than the storage capacitor Cs of the central pixel P2.
[0088] In this configuration, the peripheral pixel P1 with a large storage capacitance Cs is less susceptible to the influence of the parasitic capacitance (C...
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