30results about How to "Lower interconnect resistance" patented technology

The invention belongs to the technical field of high-integration encapsulation, and particularly discloses a silicon slice alignment method for silicon through hole interconnection. The method comprises that: stacked and interconnected upper and lower silicon slices are aligned and corrected by adopting an electric method when a plurality of silicon slices are stacked and interconnected, so the alignment precision of the silicon slices can be improved and the interconnected resistance can be reduced. The integrated circuit chip manufactured by the method has the performance of high speed and low power consumption.

The invention discloses an integrated circuit module and a packaging assembly of the integrated circuit module. The integrated circuit module comprises a semiconductor bare chip, a first insulation layer and i power buses, wherein the semiconductor bare chip comprises a plurality of electronic devices which are divided into m sets, each electronic device comprises n electrodes with different polarities, and m and n are both integers larger than one; the first insulation layer is located on the surface of the semiconductor bare chip; the i power buses comprise a plane extending portion located on the first insulation layer and a plurality of perpendicular channel portions which penetrate through the first insulation layer and are connected with all electrodes of the devices, i is an integer larger than one and smaller than or equal to m*n, one electrode of each device in at least two electronic devices and one electrode of another device in at least two electronic devices are electrically connected through at least one power bus among the i power buses, and each power bus among the i power buses is connected to an external connecting terminal. By the adoption of the integrated circuit module, a lead frame with a finger-shaped lead fin is omitted, so that the design of the lead frame is simplified, the interconnection resistance is reduced, and heat dissipation performance is improved.

The invention discloses a method for realizing high-performance copper interconnection by using an upper mask, comprising a semiconductor substrate with a metal interconnection layer, wherein a composite structure is formed on the metal interconnection layer of the semiconductor substrate from bottom to top The etching stop layer, the dielectric layer, the overlying layer, the etching adjustment layer and the mask layer are in sequence, and the etching adjustment layer is a thin film of low dielectric constant material. The beneficial effects of the present invention are: through the technological process and method of the present invention, the added low dielectric constant material is used to etch the depth adjustment layer, and the depth of the copper interconnection groove is selectively changed, so that the qualified specific The square resistance of the copper interconnection wires in the area is reduced, thereby achieving the purpose of selectively reducing the interconnection resistance of the chip. Through the application of the present invention, the interconnection resistance can be reduced to the greatest extent without changing the overall copper interconnection depth, without increasing the difficulty of the process, and without narrowing the process window, thereby reducing the signal delay of the chip, reducing loss, and improving the overall performance of the chip. performance.

The invention discloses a surface mounting type semiconductor resistance bridge encapsulation structure. The encapsulation structure comprises a semiconductor resistance bridge chip, three layers of metal electrodes and an insulating glue layer; two leading end bonding pads of the semiconductor resistance bridge chip respectively have a solder plating coating layer; and every metal electrode has asolder plating coating layer. The leading end bonding pads of the semiconductor resistance bridge chip and the top metal electrode are thermocompression-bonded through the solder plating coating layers, the top metal electrode and the top metal electrode are thermocompression-bonded through the solder plating coating layers, and the middle metal electrode and the bottom metal electrode are thermocompression-bonded through the solder plating coating layers; and the semiconductor resistance bridge chip and the bottom metal electrode are bond-reinforced through epoxy and other insulating glues.The encapsulation structure uses the molded metal plate thermocompression-bonded structure with three solder plating coating layers to substitute substrate and chip bonding, metal leading wire bondingand encapsulation structure in the semiconductor resistance bridge, so the encapsulation structure has the advantages of simple structure, low encapsulation interconnection resistance, thinness in encapsulation, few encapsulation process steps, small device investment, and is suitable for thin and standardized surface mounting, low-cost and high-reliability requirements of the semiconductor resistance bridges in automobile airbags, automobile emergency hammers and digital electronic detonators.

The invention discloses a semiconductor structure with a heavy wiring layer and a manufacturing method thereof. The semiconductor structure with the heavy wiring layer comprises a chip with an active surface, a first connecting pad and a second connecting pad which are positioned on the active surface, a passivation layer positioned on the active surface, and the heavy wiring layer positioned on the passivation layer, wherein the heavy wiring layer is electrically connected with the first connecting pad and the second connecting pad which are used for educing electrodes of an element inside the chip, and a part of the second connecting pad is exposed as an interconnecting welding area for achieving interconnection with the outside so as to enable an interconnecting welding area originally at the first connecting pad of the chip to be rearranged at the exposed second connecting pad and directly used as the interconnecting welding area, so that the integration degree and the layout flexibility of the chip are improved and the interconnecting resistance during chip packaging is reduced; the semiconductor structure with the heavy wiring layer is relatively simple, so that reduction in manufacturing processes and reduction in production cost are facilitated.

The invention provides a copper interconnection structure manufacturing method, copper interconnection structure and electronic device wherein the manufacturing method comprises: providing a semiconductor substrate; forming on the semiconductor substrate an interlayer dielectric layer with groove; forming on the side wall of the groove a dielectric barrier layer; forming on the dielectric barrier layer a conductive barrier layer; and filling copper into the remaining part of the groove to form the copper interconnection structure. According to the copper interconnection structure manufacturing method provided by the invention, through the use of two barrier layers of the dielectric barrier layer and the conductive barrier layer, it is possible to ensure certain resistance capability and prevent copper from spreading to the dielectric barrier layer; and at the same time, it is possible to properly reduce the thickness of the conductive barrier layer so that the thickness of the copper layer for interconnection is increased in relative, therefore, further reducing the interconnection resistance and increasing the optical performance of a component.

The invention provides a multilayer interconnection packaging structure of an embedded microwave multi chip with a silicon chip as a substrate and a manufacturing method. The invention is characterized by utilizing the low-cost silicone chip as the chip embedded substrate and using wire bonding and ball mounting technology to prepare gold bumps, realizing short-distance interconnection between microwave chips, using a low-k liquid or colloidal polymer as a dielectric layer, realizing the multilayer interconnection structure of a metal / organic polymer by combining wafer level processing technics such as photoetching, electroplating, chemical mechanical polishing and the like and realizing system integration of active and passive devices. The whole packaging structure has higher packaging integration and lower high-frequency transmission loss. The structure can effectively integrate varied function device units, reduce the interconnection loss among the devices and improve the properties of the whole module while improving the density and integration of packaging and reducing the cost of packaging.

The invention discloses an interconnection structure of semiconductors and a formation method. The interconnection structure of the semiconductors comprises a metal interconnecting layer including a metal layer and a first metal protrusion connected with the edges of the metal layer and a conductive plug arranged on the surface of the first metal protrusion, wherein the distance between the conductive plug and the point of the first metal protrusion is larger than the minimum design size. When the temperature of the semiconductor interconnection structure drops from high manufacturing technique temperature to room temperature, the portions, corresponding to the parts from the conductive plug to the point of the first metal protrusion and from the conductive plug to the metal edge, of the first metal protrusion shrink, produced stresses are cancelled out, and thus the positions of the conductive plug and the metal protrusion do not missed relatively, and no gaps are formed at the contacting position of the conductive plug and the metal protrusion.