4results about How to "Lower interconnect resistance" patented technology

The present invention provides a packaging structure suitable for a power converter, wherein a first power transistor and a control and drive circuit are integrated into the same chip, which can better realize the high-frequency switching action of the first power transistor, increase the operating frequency of the first power transistor, and reduce the switching loss. The second power transistor is integrated into an independent second chip, and the first chip and the second chip are separated in the packaging structure. The control and drive action of the second power transistor will not interfere with or have other negative effects on the first chip, thereby improving reliability. The first chip and the second chip can be connected through a large-area connection structure, achieving a lower interconnection resistance and improving the large current handling capability.

The invention relates to the technical field of power supply anti-reversion devices, and discloses an SIP packaged power supply anti-reversion device and a packaging manufacturing method thereof, and the power supply anti-reversion device comprises a first electrode, a second electrode, a ceramic metal substrate, a plurality of bare Mos chips, and a printed circuit board provided with a passive device. According to the invention, the bare Mos chip is adopted to replace a discrete Mos chip adopted by a known power supply anti-reversion device in the prior art, so that the manufacturing cost of the power supply anti-reversion device is reduced, and the heat dissipation capability of the power supply anti-reversion device is improved; according to the invention, the copper clamp is used as an interconnection structure between two adjacent bare core Mos chips, and the interconnection resistance between the two bare core Mos chips can be effectively reduced, so that the conduction resistance can be reduced, and the heating and power consumption of the bare core Mos chips can be reduced; the SIP packaging scheme is adopted to package and manufacture the power supply anti-reversion device, which is more beneficial to the compact and miniaturized design of the power supply anti-reversion device.

The application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a preparation method thereof, which comprises a semiconductor substrate, a first transistor and a second transistor, the first transistor and the second transistor are sequentially arranged above the semiconductor substrate along the thickness direction of the semiconductor substrate from bottom to top, the first transistor comprises a first gate stack structure and a first source / drain region located on both sides of the first gate stack structure, the second transistor comprises a second gate stack structure and a second source / drain region located on both sides of the second gate stack structure, a gate isolation structure is arranged between the first gate stack structure and the second gate stack structure, and a source / drain isolation region is arranged between the first source / drain region and the second source / drain region; wherein, in the width direction of the channel, the width of the gate isolation structure and the width of the source / drain isolation region are the same; and the first source / drain region and the second source / drain region are respectively located below and above the source / drain isolation region. The application significantly reduces the process integration difficulty of the device.

This application discloses a hybrid interposer and a method for forming the same. The method includes: providing a glass interposer, the glass interposer including a plurality of discrete functional regions and a cut-out region located between adjacent functional regions, the glass interposer including opposing first and second surfaces; forming a first bonding layer on the first surface of the glass interposer; providing a plurality of silicon interposers, each silicon interposer including opposing third and fourth surfaces, the third surface having a second bonding layer; bonding at least one silicon interposer to each functional region of the glass interposer, such that the second bonding layer and the first bonding layer are mixed-bonded; and forming a molding compound covering the silicon interposers on the first surface of the glass interposer, the molding compound exposing the fourth surface of the silicon interposers. This method improves the size and interconnect density of the interposer and reduces the warpage of the interposer.