30results about How to "Lower interconnect resistance" patented technology

Interconnects for integrated circuits, such as damascene structures are formed using a hard mask. The hard mask is formed from, for example, high-k dielectric material such as hafnium oxide or other materials having high etch selectivity to the interconnect dielectric material. This enables a thin mask to etch vias and trenches in the interconnect dielectric layer, avoiding the problems associated with the use of thick mask layers, such as contact hole striations and small depth of focus, which can result in shorts or opens.

A p-type MIS transistor includes a first gate insulating film formed on a first active region; and a first fully silicided gate pattern that is obtained by fully siliciding a silicon film, is formed to extend over the first active region with the first gate insulating film sandwiched therebetween, and includes a first fully silicided gate electrode provided on the first active region and a first fully silicided gate line provided on the isolation region. The first fully silicided gate pattern includes, along a gate width direction, a portion having a first thickness and including the first fully silicided gate electrode and portions each having a second thickness larger than the first thickness and respectively disposed on both sides of the portion having the first thickness.

It is an object of the present invention to provide a photovoltaic module capable of reducing an area occupied by interconnectors. The photovoltaic module of the present invention comprises light-transmitting substrate, strings including a plurality of solar cells interconnected through tab connector, and rear surface member. A plurality of the strings is electrically connected through interconnectors and arranged on a rear surface side so as not to overlap each other. The photovoltaic module is sealed with a sealant between the light-transmitting substrate and the rear surface member.

The invention discloses an electroplating copper solution and electroplating method for a wafer-level packaging super TSV copper interconnection material. The electroplating copper solution comprises,according to the concentration, 100-250 g/L of concentrated copper sulfate pentahydrate, 40-80 g/L of concentrated sulfuric acid, 30-50 mg/L of chloride ions, 1-5 mg/L of 3-sulfur-isothiourea propanesulfonic acid inner salt, 50-100 mg/L nonylphenol polyoxyethylene ether, 40-80 mg/L of phenazine dye and the balance DI pure water; the components are uniformly mixed to form the electroplating coppersolution; before electroplating, the wafer is subjected to vacuum treatment by a pretreatment solution; the pretreatment solution is DI pure water, and the wafer is vacuumized by using DI pure waterin vacuum equipment for 5-10 min after the wafer is mounted by an electroplating hanger; and after vacuumizing, electroplating is carried out in the electroplating copper solution. The super TSV growsin the bottom-up form, so that the problems of voids, cracks and the like of existing super TSV are solved, and the defects of unstable signal transmission, large resistance, excessive power loss andthe like due to voids can be effectively avoided.

The invention discloses a semi-conductor device which comprises a substrate, a source drain region in the substrate, a grid stacking structure on the substrate, a grid lateral wall, first metal silicide in the source drain region, contact plugs arranged above the source drain region and the grid stacking structure respectively and an interlayer dielectric layer. The semi-conductor device is characterized in that second metal silicide is arranged on the first metal silicide and the grid stacking structure, and the contact plugs are contacted with the second metal silicide. By means of the semi-conductor device, by lifting the first metal silicide, the first metal silicide is higher than the surface of the source drain region, and use amount of W in a contact hole is reduced. Interconnection resistance is greatly reduced, Cu diffusion can be effectively resisted, and the electrical performance of the device is effectively improved on the whole.

The related preparation method for contact hole plug and first layer metal comprises: on the wafer with transistor, depositing metal front-media layer and the first metal intermediate layer; photo etching the contact hole, filling the hole with organic, and flattening the organic; photo etching the first metal groove, depositing the diffusion-barrier layer, electrochemical depositing copper, and chemical-mechanical polishing to form the plug and first layer metal. This invention overcomes defects in prior art, reduces product size, and simplifies procedure for higher efficiency.

The invention provides an inverted lead frame and a packaging structure thereof, belonging to the technical field of chip packaging. The inverted lead frame comprises a first area part corresponding to a position at which a chip to be packaged is placed. The pins of the lead frame are arranged in the first area part at a position corresponding to the position of the pad of the chip on the approximately same plane. The lead frame has the advantages that the structure is simple and compact, the cost is low, the size of the packaging structure formed by the lead frame is small and the packaging requirement of high-output-current chips can be satisfied especially.

The invention discloses a method for achieving high-performance copper interconnection by utilizing an upper mask. The method is characterized in that a semiconductor substrate with a metal interconnection layer is arranged, wherein a composite structure is formed on the metal interconnection layer of the semiconductor substrate and comprises an etch stop layer, a dielectric layer, an upper coating, an etch adjustment layer and a mask layer from bottom to top in sequence; and the etch adjustment layer is made of a low dielectric constant material film. The invention has the following beneficial effects: through the process flow and method disclosed by the invention, the added low dielectric constant material etch depth adjustment layer is utilized to selectively change the depth of the grooves of copper interconnection lines, thus reducing the square resistance of the copper interconnection lines which conform to the conditions and are arranged in the specific region, and further achieving the aim of selectively reducing the chip interconnection resistance; and by utilizing the method, the interconnection resistance can be furthest reduced on the premises of not changing the overall copper interconnection depth, not increasing the process difficulty and not reducing the process window, thus reducing the signal delay of the chips, reducing the losses and improving the overall performance of the chips.

The invention discloses a semiconductor device and a preparation method thereof. The preparation method of the semiconductor device comprises the following steps: providing a to-be-filled layer; forming a patterned mask layer on the upper surface of the to-be-filled layer, and etching the to-be-filled layer based on the mask layer to form a to-be-filled pattern; forming a filling layer in the to-be-filled pattern and on the upper surface of the mask layer; etching the filling layer by taking the mask layer as an etching barrier layer, so that the filling layer is flush with the surface of the mask layer; and removing the mask layer. The mask layer is used as the etching barrier layer to etch the filling layer, so that the filling layer is flush with the surface of the mask layer, the redundant filling layer can be prevented from being removed in a mechanical mode, and defects are avoided.

The invention discloses a method for realizing a high-performance copper interconnection by an upper mask, comprising a semiconductor substrate with a metal interconnection layer, wherein a compound structure is formed on the metal interconnection layer of the semiconductor substrate, and orderly comprises an etching stop layer, a dielectric layer, an overlying layer and a mask layer from bottom to top. The method for realizing a high-performance copper interconnection by an upper mask disclosed by the invention has the following advantage that: via the technique process and method disclosed by the invention, an added titanium nitride metal hard mask is used as an etching depth adjustment layer for selectively changing the depth of the ditch of a copper interconnection line, so as to reduce the square resistance of the copper interconnection line in a specific area satisfying conditions, thereby realizing a purpose of selectively reducing a chip interconnection resistance. Via the application of the method disclosed by the invention, the interconnection resistance can be furthest reduced on the premise that the whole copper interconnection depth is not changed, the technique difficulty is not increased, and the technique window is not reduced, thereby reducing the signal delay of a chip, reducing loss, and improving the whole performance of the chip.

The invention discloses a metal diffusion barrier layer structure. The metal diffusion barrier layer structure comprises an adhesion layer, a molybdenum disulfide barrier layer, a seed crystal layer and a wire layer which are sequentially formed in a groove or a hole from outside to inside, wherein the molybdenum disulfide barrier layer is formed by permeating sulfur into the copper-molybdenum alloy seed crystal layer and reacting the sulfur with molybdenum in the copper-molybdenum alloy seed crystal layer. The three-dimensional molybdenum disulfide layer is used for replacing traditional tantalum nitride to serve as the metal diffusion barrier layer, the thickness of the barrier layer can be greatly reduced, the proportion of wire metal is increased, good electrical conductivity is achieved, and therefore the metal interconnection resistance can be greatly reduced on the whole, the electromigration resistance of the copper wire is improved, and the problems of groove coverage rate, process compatibility and the like due to introduction of a two-dimensional material in a subsequent process are effectively solved.

The invention discloses a method for realizing high-performance copper interconnection by using an upper mask. The upper mask comprises a semiconductor substrate with a metal interconnecting layer, wherein a composite structure is formed on the metal interconnecting layer of the semiconductor substrate; the composite structure consists of an etching stop layer, a medium layer, an upper coating layer, an etching adjusting layer and a mask layer from bottom to top; and the etching adjusting layer is a silicon oxide thin film. The method has the advantages that: according to the technical flow and the method provided by the invention, the depth of a copper interconnecting line ditch is selectively changed by using the added silicon oxide to etch a depth-adjusting layer, so the square resistance of a copper interconnecting line which is in accordance with a condition in a specific area is reduced, and the aim of selectively reducing chip interconnecting resistance is fulfilled. According to the application of the method, the interconnecting resistance can be reduced to the great extent on the premise that the overall copper interconnection depth is not changed, the process difficulty is not increased, and the size of a technical window is not reduced, the signal delay of a chip is reduced, the loss is reduced, and the overall performance of a chip is improved.