Method for realizing high-performance copper interconnection by upper mask

Abstract

The invention discloses a method for realizing a high-performance copper interconnection by an upper mask, comprising a semiconductor substrate with a metal interconnection layer, wherein a compound structure is formed on the metal interconnection layer of the semiconductor substrate, and orderly comprises an etching stop layer, a dielectric layer, an overlying layer and a mask layer from bottom to top. The method for realizing a high-performance copper interconnection by an upper mask disclosed by the invention has the following advantage that: via the technique process and method disclosed by the invention, an added titanium nitride metal hard mask is used as an etching depth adjustment layer for selectively changing the depth of the ditch of a copper interconnection line, so as to reduce the square resistance of the copper interconnection line in a specific area satisfying conditions, thereby realizing a purpose of selectively reducing a chip interconnection resistance. Via the application of the method disclosed by the invention, the interconnection resistance can be furthest reduced on the premise that the whole copper interconnection depth is not changed, the technique difficulty is not increased, and the technique window is not reduced, thereby reducing the signal delay of a chip, reducing loss, and improving the whole performance of the chip.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for realizing high-performance copper interconnection by using an upper mask. Background technique [0002] In the semiconductor integrated circuit industry, high-performance integrated circuit chips require high-performance back-end electrical connections. Due to its low resistivity properties, metallic copper has been more and more widely used in advanced integrated circuit chips. From aluminum wires to copper wires, the material change brought about a huge reduction in resistivity. With the advancement of integrated circuit technology, the complexity of the chip increases, which means that the resistance of the back-end interconnection lines in the chip becomes one of the bottlenecks of performance. How to effectively reduce the resistance has become an important research topic for back-end interconnection. [0003] From the resistance formula, we can get...

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Problems solved by technology

Because the thickness is too thick, it means that the depth of the trench structure is very large, which will not be conducive to the etching process to control the shape and size of the etching, and the metal filling process is also difficult to complete the complete filling, which will increase the resistance and reduce the interconnection. reliability, with a very detrimental effect on

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