A Method of Realizing High Performance Copper Interconnection Using Upper Mask

Abstract

The invention discloses a method for realizing high-performance copper interconnection by using an upper mask, comprising a semiconductor substrate with a metal interconnection layer, wherein a composite structure is formed on the metal interconnection layer of the semiconductor substrate from bottom to top The etching stop layer, the dielectric layer, the overlying layer, the etching adjustment layer and the mask layer are in sequence, and the etching adjustment layer is a thin film of low dielectric constant material. The beneficial effects of the present invention are: through the technological process and method of the present invention, the added low dielectric constant material is used to etch the depth adjustment layer, and the depth of the copper interconnection groove is selectively changed, so that the qualified specific The square resistance of the copper interconnection wires in the area is reduced, thereby achieving the purpose of selectively reducing the interconnection resistance of the chip. Through the application of the present invention, the interconnection resistance can be reduced to the greatest extent without changing the overall copper interconnection depth, without increasing the difficulty of the process, and without narrowing the process window, thereby reducing the signal delay of the chip, reducing loss, and improving the overall performance of the chip. performance.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for realizing high-performance copper interconnection by using an upper mask. Background technique [0002] In the semiconductor integrated circuit industry, high-performance integrated circuit chips require high-performance back-end electrical connections. Due to its low resistivity properties, metallic copper has been more and more widely used in advanced integrated circuit chips. From aluminum wires to copper wires, the material change brought about a huge reduction in resistivity. With the advancement of integrated circuit technology, the complexity of the chip increases, which means that the resistance of the back-end interconnection lines in the chip becomes one of the bottlenecks of performance. How to effectively reduce the resistance has become an important research topic for back-end interconnection. [0003] From the resistance formula, we can get...

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Problems solved by technology

Because the thickness is too thick, it means that the depth of the trench structure is very large, which will not be conducive to the etching process to control the shape and size of the etching, and the metal filling process is also difficult to complete the complete filling, which will increase the resistance and reduce the interconnection. reliability, with a very detrimental effect on

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