[0029] The features and technical effects of the technical solutions of the present invention are described in detail below with reference to the accompanying drawings and schematic embodiments, and a semiconductor device and a manufacturing method thereof that can effectively reduce interconnect resistance are disclosed. It should be noted that similar reference numerals denote similar structures, and the terms "first", "second", "upper", "lower", etc. used in this application may be used to modify various device structures or fabrication processes . These modifications do not imply a spatial, sequential, or hierarchical relationship of the modified device structures or fabrication processes unless otherwise specified.
[0030] First, refer to image 3 , forming contact holes in the base structure.
[0031] Specifically, the substrate 10 is provided first. The substrate 10 may be bulk silicon, silicon-on-insulator (SOI), or a compound semiconductor substrate such as SiGe, SiC, etc., and combinations of these, but preferably includes elemental silicon. The substrate 10 may be intrinsic or doped with low concentrations of impurities to control its electrical properties, such as n-doping or p-doping. A trench is formed in the substrate 10 by photolithography/etching, and then an insulating material such as silicon oxide and silicon oxynitride is filled by conventional methods such as LPCVD, PECVD, and HDPCVD to form an isolation structure 11 in the form of shallow trench isolation. The substrate 10 surrounded by the isolation structure 11 forms an active region, preferably a well region (not shown), such as a p+ well region or an n+ well region, can be formed by doping another impurity with a polarity different from that of the doping impurity of the substrate 10 well area.
[0032] The source and drain regions 20 are formed in the substrate 10 , and the gate stack structure 40 is formed on the substrate 10 . For the gate-last process, a pad layer (not shown) such as silicon oxide and a dummy gate (not shown) such as polysilicon are sequentially deposited on the substrate 10 and etched to form a dummy gate stack. Then, using the dummy gate stack structure as a mask, the first source-drain ion implantation is performed, and a small impurity dose and implantation energy are selected to form lightly doped source-drain regions or source-drain extension regions 21 in the substrate 10, Its conductivity type is opposite to that of the substrate 10 or the well region of the active region. Next, an insulating film such as silicon nitride or silicon oxynitride is deposited on the entire device, and the gate spacers 30 are formed by etching only on both sides of the dummy gate stack structure. Using the gate spacer 30 as a mask, the second source-drain ion implantation is performed, and a larger impurity dose and implantation energy are selected to form heavily doped source and drain regions 22 and lightly doped source and drain regions 21 in the substrate 1 The source and drain regions 20 are formed together with the heavily doped source and drain regions 22 . Then, the dummy gate and pad layer of polysilicon are removed with a wet etching solution such as TMAH, leaving a gate trench exposing the substrate 10, and then a gate insulating layer 41 and a gate conductive layer are sequentially deposited in the gate trench 42 , forming a gate stack structure 40 , wherein the gate insulating layer 41 surrounds the gate conductive layer 42 . The material of the gate insulating layer 41 is a high-k material, including but not limited to nitrides (such as SiN, AlN, TiN), metal oxides (mainly oxides of subgroup and lanthanide metal elements, such as Al 2 O 3 , Ta 2 O 5, TiO 2 , ZnO, ZrO 2 , HfO 2 , CeO 2 , Y 2 O 3 , La 2 O 3 ), perovskite phase oxides (such as PbZr x Ti 1-x O 3 (PZT), Ba x Sr 1-x TiO 3 (BST)). The material of the gate conductive layer 42 includes polysilicon (doped), metal, metal alloy, and metal nitride, wherein the metal may include Al, Ti, Cu, W, Au, Ag, and the like.
[0033] An interlayer dielectric layer (ILD) 50 is deposited on the substrate 10 and the gate stack structure 40 by conventional methods such as CVD, and the material thereof includes oxide, oxynitride, and the oxide is PSG, for example.
[0034] The ILD 50 is photolithographically/etched until the gate stack structure 40 and the source and drain regions 20 are exposed, and contact holes 51 are formed, including the source and drain contact holes 51A and the gate contact holes 51B.
[0035] Second, refer to Figure 4 , a first metal silicide 61 is formed in the source-drain contact hole 51A. A thin metal layer (not shown) is deposited on the entire basic structure by means of, for example, sputtering or evaporation, as a precursor for the first metal silicide, which is made of Ni, Pt or its alloy NiPt (with a Pt content of less than equal to 10%). The entire structure is annealed at 500° C. to 850° C. and the unreacted metal layer is stripped, so that the metal in the metal layer reacts with the silicon in the surface portion of the heavily doped source and drain regions 22 to grow and form a first metal silicide 61. Depending on the material of the metal layer, the material of the first metal silicide 61 to be formed may include NiSi, NiSi 2 , NiPtSi, NiPtSi 2. Since the process of forming the first metal silicide 61 is formed by the reaction of the metal with the silicon of the source and drain regions 20 and partially consumes the silicon, the top surface of the first metal silicide 61 generally does not substantially exceed the top surface of the source and drain regions 20 , Or the height of the excess is only about 2 nm, in other words, the first metal silicide 61 is substantially flush with the top surface of the source and drain regions 20 . The existence of the first metal silicide 61 effectively reduces the source-drain contact resistance.
[0036] Then, refer to Figure 5 , a second metal silicide 62 is formed in the source-drain contact hole 51A and the gate contact hole 51B. Similar to the formation of the first metal silicide 61, metal material and silicon material are deposited on the entire structure as precursors, and then annealed at 500° C. to 850° C. and unreacted material is stripped, so that the metal material and the silicon material are completely The reaction generates the second metal silicide 62 . Similar to the above, the metal material can be Ni, Pt or an alloy thereof, and the second metal silicide 62 formed can be of the same or different material as the first metal silicide 61 . The steps of depositing the metal material and the silicon material may be two separate depositions (eg depositing metal first and then depositing silicon, or first depositing silicon and then depositing metal), or may be one co-deposition, such as co-sputtering. According to different device resistance performance requirements, the process steps of forming the second metal silicide 62 may be performed multiple times until the thickness of the second metal silicide 62 meets the requirements. Preferably, the thickness of the portion 62A of the second metal silicide 62 in the source-drain contact hole 51A exceeds half of the height of the gate stack structure 40 . More preferably, the top surface of the second metal silicide 62 is substantially flush with the top surface of the gate stack structure 40 , or the distance from the top surface of the gate stack structure 40 is less than or equal to 10 nm. In addition, the top surface of the second metal silicide 62 may also exceed the top surface of the gate stack structure 40, which will further reduce the resistance. The metal silicide 60 thus formed includes the first metal silicide 61 and the second metal silicide 62, and has a raised surface, that is, much higher than the source and drain regions 20, so that the amount of W in the contact hole can be reduced, not only can The interconnect resistance is greatly reduced, and the Cu diffusion can be effectively blocked to improve device performance.
[0037] Finally, refer to Image 6 , the filling metal forms the contact plug 70 . A first metal such as W is deposited in the source-drain contact hole 51A and the gate contact hole 51B to form a first contact plug 71 whose top surface is preferably flush with the top surface of the gate stack structure 40 . In particular, when the top surface of the second metal silicide 62 in the source-drain contact hole 51A is higher than the gate stack structure 40, the first contact plug 71 of the W material may also be higher than the gate stack structure 40 or may be omitted. A second metal, such as Cu, is deposited on the first contact plug 71 to form a second contact plug 72, and a CMP planarization process is performed so that the top surface of the final contact plug is substantially flush with the top surface of the ILD 50.
[0038] The final device structure is as Image 6 As shown, it includes the substrate 10, the source and drain regions 20 in the substrate 10, the gate stack structure 40 and the gate spacers 30 on the substrate 10, the first metal silicide 61 in the source and drain regions 20, and the contact plug 70 and the interlayer dielectric layer 50 are characterized in that: the first metal silicide 61 has a second metal silicide 62 , and the contact plug 70 is in contact with the second metal silicide 62 . Wherein, the top surface of the metal silicide 61/62 is higher than the top surface of the substrate 10, specifically, the thickness of the second metal silicide 62 is preferably greater than 50% of the thickness of the gate stack structure 40, and preferably its top The distance between the surface and the top surface of the gate stack structure 40 is less than or equal to 10 nm. The material of the first and/or second metal silicide includes NiSi, NiSi 2 , NiPtSi, NiPtSi 2. The contact plug 70 sequentially includes a first contact plug 71 of material W located below and a second contact plug 72 of material Cu located above. Preferably, the top surface of the second contact plug 72 above the source and drain regions 20 is flush with the top surface of the gate stack structure 40 .
[0039] According to the semiconductor device of the present invention, by raising the metal silicide to make it higher than the surface of the source and drain regions, the amount of W in the contact hole can be reduced, which can not only greatly reduce the interconnection resistance but also effectively block the diffusion of Cu, so that the overall effective The electrical performance of the device is improved.
[0040] Although the invention has been described with reference to one or more exemplary embodiments, those skilled in the art will recognize various suitable changes and equivalents in device structure without departing from the scope of the invention. In addition, many modifications, as may be adapted to a particular situation or material, may be made from the disclosed teachings without departing from the scope of the invention. Therefore, the present invention is not intended to be limited to the particular embodiments disclosed as the best mode for carrying out the present invention, and the disclosed device structures and methods of making the same are to include all embodiments that fall within the scope of the present invention .
