Method for achieving high-performance copper interconnection by utilizing upper mask

Abstract

The invention discloses a method for achieving high-performance copper interconnection by utilizing an upper mask. The method is characterized in that a semiconductor substrate with a metal interconnection layer is arranged, wherein a composite structure is formed on the metal interconnection layer of the semiconductor substrate and comprises an etch stop layer, a dielectric layer, an upper coating, an etch adjustment layer and a mask layer from bottom to top in sequence; and the etch adjustment layer is made of a low dielectric constant material film. The invention has the following beneficial effects: through the process flow and method disclosed by the invention, the added low dielectric constant material etch depth adjustment layer is utilized to selectively change the depth of the grooves of copper interconnection lines, thus reducing the square resistance of the copper interconnection lines which conform to the conditions and are arranged in the specific region, and further achieving the aim of selectively reducing the chip interconnection resistance; and by utilizing the method, the interconnection resistance can be furthest reduced on the premises of not changing the overall copper interconnection depth, not increasing the process difficulty and not reducing the process window, thus reducing the signal delay of the chips, reducing the losses and improving the overall performance of the chips.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for realizing high-performance copper interconnection by using an upper mask. Background technique [0002] In the semiconductor integrated circuit industry, high-performance integrated circuit chips require high-performance back-end electrical connections. Due to its low resistivity properties, metallic copper has been more and more widely used in advanced integrated circuit chips. From aluminum wires to copper wires, the material change brought about a huge reduction in resistivity. With the advancement of integrated circuit technology, the complexity of the chip increases, which means that the resistance of the back-end interconnection lines in the chip becomes one of the bottlenecks of performance. How to effectively reduce the resistance has become an important research topic for back-end interconnection. [0003] From the resistance formula, we can get...

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Problems solved by technology

Because the thickness is too thick, it means that the depth of the trench structure is very large, which will not be conducive to the etching process to control the shape and size of the etching, and the metal filling process is also difficult to complete the complete filling, which will increase the resistance and reduce the interconnection. reliability, with a very detrimental effect on

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