Manufacturing method of copper interconnection structure, copper interconnection structure and electronic device

Abstract

The invention provides a copper interconnection structure manufacturing method, copper interconnection structure and electronic device wherein the manufacturing method comprises: providing a semiconductor substrate; forming on the semiconductor substrate an interlayer dielectric layer with groove; forming on the side wall of the groove a dielectric barrier layer; forming on the dielectric barrier layer a conductive barrier layer; and filling copper into the remaining part of the groove to form the copper interconnection structure. According to the copper interconnection structure manufacturing method provided by the invention, through the use of two barrier layers of the dielectric barrier layer and the conductive barrier layer, it is possible to ensure certain resistance capability and prevent copper from spreading to the dielectric barrier layer; and at the same time, it is possible to properly reduce the thickness of the conductive barrier layer so that the thickness of the copper layer for interconnection is increased in relative, therefore, further reducing the interconnection resistance and increasing the optical performance of a component.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. Background technique [0002] With the development of semiconductor technology, integrated circuits are gradually developing towards ultra-large-scale integrated circuits (ULSI), and the feature size of the internal circuits is getting smaller and smaller, the density is getting higher and higher, and the number of components contained is increasing. With its excellent conductivity, copper has become one of the solutions for interconnection integration technology in the field of integrated circuit technology. [0003] In the copper interconnection process of the back-end process (BEOL), as the size of the device shrinks, the volume of copper used for interconnection is also reduced, and the reduction in copper volume and the size effect will cause the interconnection resistance to inc...

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Problems solved by technology

[0003] In the copper interconnection process of the back-end process (BEOL), as the size of the device shrinks, the volume of copper used for interconnection is also reduced, and the reduction in copper volume and the size effect will cause the interconnection resistance to increase, and the device Electrical degradation issues (i.e., increased RC delay)

In order to reduce the increase in interconnect resistance due to the reduction in copper volume and size effects, various methods have been tried, one of the most promising methods is to reduce the metal liner between the copper and the dielectric layer. thickness, but this approach requires the introduction of materials with high step coverage, high diffusion resistance to copper and ULK (ultra-low K) oxides, which are not readily available and / or or preparation

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