Method for analyzing chip failure

Abstract

The invention provides a method for analyzing chip failure, which is used for detecting defect characteristics of a chip grid and comprises the following steps: removing most of a substrate and an active region of a chip to be subjected to failure analysis through mechanical grinding; removing the remained substrate and active region of the chip through wet etching; removing most of a gate oxide layer of the chip through dry etching, wherein the remained gate oxide layer is used for protecting a first polysilicon layer of the grid; and detecting whether the defect characteristics exist on thefirst polysilicon layer or not. By utilizing the method provided by the invention, the chip can be accurately stripped to the bottom of the first polysilicon layer of the grid, the accurate size parameters of the bottom of the first polysilicon layer can be measured, the working efficiency can be greatly improved, and the time can be saved.

Description

technical field [0001] The invention relates to the field of semiconductor failure analysis, in particular to a chip failure analysis method. Background technique [0002] In the modern integrated circuit manufacturing process, chip processing needs to go through a series of chemical, optical, metallurgical, thermal processing and other process links. Each process may introduce various defects. At the same time, due to the continuous shrinking of feature size, the cost of various processing facilities has also risen sharply, so the loss caused by device defects is extremely expensive. Under such conditions, it becomes an indispensable link in the manufacture of integrated circuits to analyze the cause of failure and reduce device defects through verification testing. Through the failure analysis work, it can help IC designers find design defects and mismatch of process parameters, and also help IC application personnel find problems such as improper use of design or operat...

AI Technical Summary

Problems solved by technology

[0006] The technical problem to be solved by the present invention is to provide a chip failure analysis method to solve the problem that it is difficult to accurately and efficiently grind and strip the bottom of the first polysilicon layer of the gate to measure the accurate size parameters of the bottom in the chip failure analysis

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