A fault-tolerant architecture for
wafer-scale all-
silicon computing engines is disclosed, featuring "CREST" (Cyclic Redundant Spare Testing) and dynamic column substitution. The
system integrates a massive array of
processing elements with granular redundancy, such as spare columns and rows. A network of bypass multiplexers allows logical compute resources to be remapped to physical hardware dynamically. A redundancy controller performs background cyclic testing by
pairing active columns with spares and comparing outputs, enabling run-time detection and repair of defects without
system downtime. The architecture supports
predictive failure analysis, secure configuration updates, and hierarchical
fault management across vertically stacked dies and the
wafer-scale substrate, ensuring high yield and reliability for zetta- scale
inference workloads.