119results about How to "Reduce EMI" patented technology

Disclosed is a high-swing voltage-mode transmitter or line driver. The transmitter can operate over a wide range of supply voltages. Increasing the available output swing merely involves increasing the supply voltage; the circuit adapts to maintain the desired output impedance. This allows for a tradeoff between output amplitude and power consumption. Another advantage of the proposed architecture is that it compensates for process, voltage, and temperature (PVT) and mismatch variations so as to keep rise and fall times matched. This feature reduces common-mode noise and hence EMI in systems in which the transmitter is used.

A master-slave type flip-flop circuit consisting of a master latch and a slave latch, wherein the master latch comprises: a first clocked inverter to which data are input and a first latch circuit configuring a closed circuit with a first inverter and a second clocked inverter so that an output of the first clocked inverter is input to the first inverter and; the slave latch comprises: a transmission gate to which an output from the first latch circuit is input and a second latch circuit configuring a closed circuit with a second inverter and a third clocked inverter so that an output of the transmission gate is input to the second inverter, respective components configuring the master latch and the slave latch are configured with Sea Of Gate (hereinafter to be referred to as SOG) configuring a gate array, a basic cell of the SOG consists of triplely arrayed N-type transistors and corresponding triplely arrayed P-type transistors, the triplely arrayed N-type transistors consist of double-arrayed normally sized main transistors and one auxiliary transistor sized smaller than in a normal size and the triplely arrayed P-type transistors consist of double-arrayed normally sized main transistors and one auxiliary transistor sized smaller than in a normal size.

Circuits and methods of dynamic modulation are disclosed. A dynamic modulator is used to reduce measurable conducted and/or radiated electromagnetic interference (EMI). The dynamic modulator is configured to generate either a set of optimal frequency modulation depths or discrete frequencies or both, and dynamically selects them to use over a series of programmable time durations (dwell time). Together with the utilization of Peak, Average or Quasi-Peak (QP) method of measurement, the dynamic modulator can reduce the spectral amplitude of EMI components, in particular the lower harmonics, to effectively pass regulatory requirements. In alternative embodiments, the dynamic modulator is used in a closed loop system to continuously adjust the frequency and the duty cycle of a PWM signal to reduce conducted and/or radiated EMI.

The invention discloses a host-free parking radar system of a series structure. The system is provided with a plurality of sensors, at least one alarm, an internal network and an external network; each sensor comprises a microprocessor, a communication module, an ultrasonic sensor, a driving transmitting module and an ultrasonic receiving module; the communication module comprises a first interface module, a second interface module and an analog switch, wherein the first interface module and the second interface module are led outwards respectively to form a first terminal and a second terminal, and the analog switch is connected between the first terminal and the second terminal and enables information of the first terminal and the second terminal to be interconnected; and the first terminal of each sensor is connected with the second terminal of the adjacent sensor through the internal network to form the series structure, and the first terminal or the second terminal of the sensor positioned at the end is connected with the alarm through the external network. The host-free parking radar system has the effects of simplifying wiring harness connection, reducing vehicle body weight, reducing cost and improving the production efficiency and the installation efficiency.

An embodiment of the disclosed multichannel receiver may use a single master clock to generate (i) the sampling-clock signal that sets the sampling rate of the receiver's ADC and (ii) multiple electrical local-oscillator signals that are used in various channels of the receiver's analog down-converter to translate to intermediate frequency the RF signals received on the receiver's array of antennas. The multichannel receiver may employ a plurality of interconnected frequency dividers configured to variously divide the master-clock frequency to generate the sampling-clock signal and the multiple local-oscillator signals in a manner that causes these signals to have different respective frequencies.

The invention discloses a resonance direct current/ direct current converter and control method, it adjusts output voltage by changing conducting frequency of input switch of the resonance circuit, adjusts the shift angle of said switch according to feedback signal of load circuit to extend the output range of voltage of the resonance circuit. The invention also provides structure of the resonance direct current/ direct current converter with said method. The advantages of the invention are following: adopting frequency modulation and frequency modulation+ shift phase control mode to control the resonance direct current/ direct current converter, using frequency modulation when operating frequency of power source is low, using frequency modulation+ shift phase when operating frequency of power source is too high, the problem of resonance converter is resolved, that is problem of high operating frequency and big spoilage, and the output voltage adjustment capability of resonance circuit increased greatly, the output voltage range is extended efficiently.

An electrical connector includes an insulating body, a plurality of terminals, a plurality of shielding layers, and a plurality of insulating layers. The insulating body has a plurality of terminal-receiving holes. The shielding layers are mounted on the terminal-receiving holes. The insulating layers are mounted on the shielding layers, and the terminals are disposed in the terminal-receiving holes. Thereby, the insulating layers prevent EMI between terminals and ensure the terminals do not contact the shielding layers.

An ultra compact ring topology puts the output terminals of solid state switches physically at the center of a circuit with the switches surrounded by voltage busses. The switches are symmetrically arranged around the output bus, the voltage busses are filtered (decoupled) to ground using symmetrically positioned filter components, and lead lengths to and from the switches are minimized. Switch driver circuits are closely integrated with each switch and positioned as close as possible, each to its associated switch, and arranged symmetrically. Switches may be at cryogenic temperatures and busses and lead connectors may be superconductive.

In one embodiment, an SMPS includes a rectifier for generating an input DC voltage from an input AC voltage. A switching transistor is coupled to a primary coil of a transformer for generating power which is transferred to a second side of the transformer according to an operation of the switching transistor. A switching controller receives a feedback voltage corresponding to an output voltage, a sensing signal corresponding to a current flowing through the switching transistor, and a first signal corresponding to a voltage difference between a first electrode and a second electrode of the switching transistor. The switching controller controls an on/off operation of the switching transistor. The switching controller sets a threshold period whenever the first signal has a value greater than a reference value, thereby setting a plurality of threshold periods during operation of the switching mode power supply. For each threshold period, the switching controller turns on the switching transistor at a point after a variable delay time from a previous point at which the switching transistor was turned on.

A liquid crystal display device incorporates, within the same integrated circuit, a plurality of memories which store R, G, and B data supplied in parallel from an image source for the respective color components, a multiplexer which serially reads out the R, G, and B data stored in these memories and supplies them to the liquid crystal display unit, a mode switch, a D/A converter, and a buffer amplifier.

The invention discloses a control method for suppressing current zero-crossing fluctuation of a bus-shared single-side controllable open-winding permanent-magnet motor system. The motor system employs a common-direct-current power supply structure. A proper zero-sequence current reference value is designed and a proportional resonance controller is used to achieve an objective rapid zero crossing of the current. The system employs a full-control converter and an uncontrolled converter, so that the cost is reduced and the system capacity is increased; only one direct-current power supply is involved in the system and no isolation is needed, thereby realizing rapid zero crossing of the current. Only the control algorithm us changed and no system hardware cost needs to be increased. Compared with the traditional control method, the current zero-crossing fluctuation is reduced; the number of times of switching of the power diode is reduced; and the system EMI is also reduced. The control method is simple; and the anti-interference capability is high.

A switching controller having switching frequency hopping for a power converter includes an oscillator generating a pulse signal for determining a switching frequency of a switching signal, a maximum duty-cycle circuit generating a maximum duty-cycle signal in response to the switching signal for determining the switching frequency of the switching signal, a pattern generator generating a digital pattern code in response to a clock signal, a programmable capacitor coupled to the pattern generator and the oscillator for modulating the switching frequency of the switching signal in response to the digital pattern code, and a PWM circuit coupled to the oscillator and the maximum duty-cycle circuit for generating the switching signal in accordance with the pulse signal and the maximum duty-cycle signal. A maximum on-time of the switching signal is limited by the maximum duty-cycle signal. The switching signal is utilized to switch a transformer of the power converter.

The invention discloses a device backboard high-speed bus link layer communication protocol based on M-LVDS, adopting the variable data bit wide design, being suitable for large data volume communication of different data bandwidth requirement, adopting collision detection and lossless arbitration to compete for speaking right, adopting the priority rotate method for guaranteeing roll polling speak for each node, preventing occupying the bus for some node for a long time and supporting the hot plug function, the normal communication of other nodes on the bus is not impacted while any abnormal node drops out, the stability and reliability are high. The bus physical layer adopts M-LVDS with high-level ESD protection function, the reflection and EMI can be reduced by controlling the slew rate, the signal integrity is raised for greatly raising the system stability. The device backboard high-speed bus link layer communication protocol based on M-LVDS is used for realizing the industrial control, relay protection and high speed peer data interaction among modules in the safe automatic device, and satisfying the high real time performance, high reliability, flexible and extensible performance requirement to the protection control system for the intelligent power grid.

The invention discloses a soft driving method of a power MOSFET and a corresponding circuit. In a period from when the MOSFET starts to be electrified till a Miller platform is finished, soft driving current I1 is very small, a conduction process of the MOSFET is delayed, and EMI is reduced; when the MOSFET exits from the Miller platform, driving current and positive feedback large current I2 are superposed, the superposed large current is used to charge an MOSFET input capacitor, VGS voltage rises quickly, unnecessary charge consumption is reduced, i.e., conduction loss is reduced, and efficiency is improved; and after the VGS voltage rises to the highest driving voltage, the positive feedback large current I2 quickly reduces to zero. The method and the circuit provided by the invention achieve very good beneficial effects in reduction of an EMI effect, reduction of conduction loss and improvement of efficiency.

The invention discloses a phase-shift full-bridge converter circuit which comprises a transformer, a lead bridge arm, a lag bridge arm and an output circuit. The lead bridge arm is formed by serially connecting a first MOS tube and a second MOS tube, the connection point of the two MOS tubes is sequentially connected with one end of a primary side of the transformer through a capacitor and a resonant inductor, and the capacitor and the resonant inductor are connected in series. The lag bridge arm is formed by serially connecting a third MOS tube and a fourth MOS tube, the connection point of the two MOS tubes is connected with the other end of the primary side of the transformer, and input direct-current voltage is applied to the positions between the connection point of the first MOS tube and the second MOS tube and the connection point of the third MOS tube and the fourth MOS tube. The output circuit is composed of four rectifier diodes and an output capacitor. The voltage of the two ends of the output capacitor is output direct-current voltage. The invention further discloses a control method of the phase-shift full-bridge converter circuit. By means of the circuit and the method, full-bridge soft switching of the phase-shift full-bridge converter circuit is achieved, switching loss is reduced, and efficiency is improved.

In driving a Plasma Display Panel (PDP), when a driving operation moves from an address period to a sustain period, low-voltage driving switches of all of the scan ICs are turned on at the same time after the drain voltage and source voltage of each of them are made equal via a power recovery circuit under the condition that the outputs of the scan ICs are floating. Therefore, when the switches are turned on, no current flows therethrough, thereby making it possible to solve instability of a driving circuit and noise and EMI therein.

A control circuit having frequency hopping capability is used for reducing the EMI of a power supply. A switching circuit is coupled to a feedback circuit to generate a switching signal for regulating an output of the power supply. A first oscillator determines the switching frequency of the switching signal. A second oscillator is coupled to the first oscillator to modulate the switching frequency of the switching signal for reducing the EMI of the power supply. An output of the second oscillator controls the attenuation rate of the feedback signal of the feedback circuit. Therefore, even if the switching frequency is hopped, the output power and the output voltage can still be kept constant.

A spread spectrum clock generation apparatus includes a frequency modulator configured to generate an output clock signal, a frequency of which is variable with reference to a predetermined center frequency, by frequency-modulating an input clock signal according to a modulation profile signal; and a profile generator configured to generate a nested-modulation profile for controlling the frequency of the output clock signal, generate the modulation profile signal according to the nested-modulation profile, and output the modulation profile signal to the frequency modulator, wherein the profile generator is further configured to generate the nested-modulation profile by varying a cycle and a change range of a triangle modulation profile having a triangle waveform pattern having a pre-designated cycle and a pre-designated amplitude with reference to the center frequency in a time-frequency domain.

A timing controller includes a receiver, an internal clock generator, a first frequency converter, a first selector and a control signal generator. The receiver receives an image signal and a main clock signal having a first spread spectrum frequency from an external system, converts the main clock signal to a converted main clock signal and the image signal to a first converted image signal, and outputs the converted main clock signal as a first clock signal having a plurality of frequencies. The internal clock generator multiplies the frequencies of the first clock signal and generates a second clock signal having a frequency band within the multiplied frequencies of the first clock signal. The first frequency converter converts the second clock signal to a third clock signal having a second spread spectrum frequency. The first selector selects one of the second clock signal and the third clock signal in response to a first selection signal and outputs the selected one of the second clock signal and the third clock signal as a control clock signal. The control signal generator receives the control clock signal to generate a control signal synchronized with the control clock signal.

The present disclosure relates to a display interface device which can increase display information transmission efficiency and reduce power consumption and EMI, in which a transmission part transmits clock edge information included in a data packet of each channel at a different timing from clock edge information included in data packets of other channels. A reception part detects a clock edge of each channel from the data packet transmitted through each channel, generates an internal clock signal of each channel, synchronized with the detected clock edge, corrects a delay of each channel depending on a result of a logical operation performed on a delayed clock edge of a channel and a clock edge of another channel to further generate an internal clock signal of each channel, and restores the display information from the data packet of each channel using the internal clock signal of each channel.

The invention discloses a bridgeless electrolytic-capacitor-free low-ripple-wave high-power constant-current power supply of an LED lamp. The bridgeless electrolytic-capacitor-free low-ripple-wave high-power constant-current power supply of the LED lamp comprises an alternating-current power supply circuit, a control circuit, a coupling-out circuit and a ripple wave restraining circuit. The alternating-current power supply circuit comprises a constant-current drive chip U1, a constant-current drive chip U2, an alternating-current positive half-wave current loop and an alternating-current negative half-wave current loop, wherein the constant-current drive chip U1 and the constant-current drive chip U2 are controlled by the positive half-wave and the negative half-wave of an alternating-current power supply Uin. The current of the alternating-current positive half-wave current loop and the current of the alternating-current negative half-wave current loop both flow through a primary winding N11 and a primary winding N12 of a magnetic integration transformer TR so that an induced voltage can be generated on a secondary winding NV1 and a secondary winding NV2, and then the working voltage of the constant-current drive chip U1 and the working voltage of the constant-current drive chip U2 are provided through the control circuit. An induced secondary current is generated on a center post secondary winding N2 and is output to the loaded LED lamp through the coupling-out circuit. The ripple wave restraining circuit restrains current ripple waves. According to the bridgeless electrolytic-capacitor-free low-ripple-wave high-power constant-current power supply of the LED lamp, a bridge rectifier and an electrolytic capacitor are not adopted, so that the electric power is increased, the reliability is improved, the drive capability of the chips is improved through expanded current, the working temperature of the chips is lowered, the service life of the chips is prolonged, the constant-current precision is high, the current ripple waves are small, the LED lamp does not flicker, and the circuits meet the environmental-friendliness principle.

A class-D amplifier includes an error amplification circuit, a duty signal generator, a level selection circuit, a driver and control block and an output stage. The class-D amplifier divides peal levels of an error signal into multi-level and changes a scheme for modulating the error signal when the error signal crosses each level boundary of the multi-level thereby to have an effect such as the error signal is folded. Therefore, the class-D amplifier drives output nodes with multi-level and thus the class-D amplifier may increasing efficiency while reducing EMI.