Multichannel receiver

Abstract

An embodiment of the disclosed multichannel receiver may use a single master clock to generate (i) the sampling-clock signal that sets the sampling rate of the receiver's ADC and (ii) multiple electrical local-oscillator signals that are used in various channels of the receiver's analog down-converter to translate to intermediate frequency the RF signals received on the receiver's array of antennas. The multichannel receiver may employ a plurality of interconnected frequency dividers configured to variously divide the master-clock frequency to generate the sampling-clock signal and the multiple local-oscillator signals in a manner that causes these signals to have different respective frequencies.

Description

BACKGROUND[0001]1. Field[0002]The present disclosure relates to communication equipment and, more specifically but not exclusively, to radio-frequency (RF) receivers.[0003]2. Description of the Related Art[0004]This section introduces aspects that may help facilitate a better understanding of the disclosure. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is in the prior art or what is not in the prior art.[0005]Recent development of very high-speed, high-resolution, and high-dynamic-range linear analog-to-digital converters (ADCs) enables implementation of certain RF-receiver functions using a digital signal processor (DSP) instead of the analog RF hardware conventionally used for these purposes in the previous generation of RF receivers. However, the use of wider bandwidths, multiple spectral bands, and / or spectrum sharing introduces new challenges to the receiver design.SUMMARY OF SOME SPECIFIC EMBODIM...

AI Technical Summary

Benefits of technology

[0007]An embodiment of a disclosed multichannel receiver may use a single master clock to generate (i) the sampling-clock signal that sets the sampling rate of the receiver's ADC and (ii) multiple electrical local-oscillator signals that are used in various channels of the receiver's analog down-converter to translate to intermediate frequency the RF signals received on the receiver's array of antennas. The multichannel receiver may employ a plurality of interconnected frequency dividers configured to variously divide the master-clock frequency to generate the sampling-clock signal and the multiple local-oscillator signals in a manner that causes these signals to have different respective frequencies. The use of a single master clock may advantageously enable the multichannel receiver to have a smaller size, consume less power, and exhibit lower levels of phase noise and EMI than conventional receivers that rely on multiple PLLs to generate sampling-clock and local-oscillator signals.

Problems solved by technology

However, the use of wider bandwidths, multiple spectral bands, and / or spectrum sharing introduces new challenges to the receiver design.

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