Level-triggered D flip-flop circuit based on resistive memory

Abstract

The invention discloses a level triggered D flip-flop circuit based on a resistive memory. The level triggered D flip-flop circuit comprises an MOSFET, a first memristor, a resistor, a first phase inverter and a second phase inverter. The source electrode of the MOSFET is electrically connected with an input signal; the grid electrode of the MOSFET is electrically connected with a clock pulse signal; the drain electrode of the MOSFET is electrically connected to the positive electrode of the first memristor, one end of the resistor and the input end of the first inverter. The output end of thefirst phase inverter is electrically connected to the input end of the second phase inverter; the output end of the second phase inverter is electrically connected with an output signal; the negativeelectrode of the first memristor is electrically connected to the output end of the NAND logic circuit used for conducting auxiliary setting on the first memristor, one input end of the NAND logic circuit is electrically connected with an input signal, the other input end of the NAND logic circuit is electrically connected with a clock pulse signal, and the other end of the resistor is grounded.According to the invention, the structure of the circuit is simpler and more refined, and the layout area has greater advantages.

Description

technical field [0001] The invention relates to the field of basic circuit design of an integrated circuit memory, in particular to a level-triggered D flip-flop circuit based on a resistive memory. Background technique [0002] Level-triggered D flip-flops, also known as D-type latches, are commonly used storage units in integrated circuits. figure 1 It is the circuit diagram of the memristor-based level-triggered D flip-flop in the past. Its working principle is: when the clock pulse CP is high level 1, M1 and M2 are turned on, and P1 is turned off. The equivalent circuit diagram is as follows figure 2 shown. At this time, if the input signal D is 1, the output signal Q is 1, and since a 1-setting (low resistance state of the memristor is "1") voltage Vset is applied to both ends of the memristor ME, the memristor is in In the low-impedance state, the resistance value is RL; if the input signal D is 0, the output signal Q is 0, and since a zero-setting voltage Vclear is...

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Problems solved by technology

[0003] The above circuit utilizes the non-volatile characteristics of the memristor and the compatibility between the memristor and the CMOS process to complete the design of the level-triggered D flip-flop, but compared with the level-triggered D flip-flop of the traditional CMOS proce...

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