Sampling pulse type trigger

Abstract

The invention provides a sampling pulse type trigger comprising a first data signal input unit and a second data signal input unit, a clock signal input unit, a first signal output unit and a second signal output unit, a first NOR logic unit, a second NOR logic unit, a first charging / discharging unit, a second charging / discharging unit and a maintaining unit, wherein the first NOR logic unit is used for outputting a delay clock signal of a first gating under the control of a clock signal, a first signal and a second signal; the second NOR logic unit is used for outputting a delaying clock signal of a second gating under the control of the clock signal, the first signal and the second signal; the first charging / discharging unit is used for carrying out condition sampling on a first data signal when the clock signal and the clock signal of the first gating are high electrical levels; the second charging / discharging unit is used for carrying out the condition sampling on a second data signal when the clock signal and the clock signal of the second gating are the high electrical levels; and the maintaining unit is used for switching off an upper maintaining access or a lower maintaining access of the first signal. The trigger not only has a flexible edge property, but also reduces the power consumption.

Description

technical field [0001] The invention relates to the technical field of flip-flop circuit design, in particular to a sampling pulse type flip-flop. Background technique [0002] In synchronous digital systems, more and more flip-flops are inserted into the data path to interrupt the data path to increase the system clock frequency, thereby improving system performance. This makes the design of flip-flops more and more influential on the system. This impact is mainly reflected in the following three aspects: First, the power consumption of the flip-flop accounts for an increasing proportion of the power consumption of the clock network, and the power consumption of the clock network is an important part of the total power consumption of the system, so the power consumption of the flip-flop The impact on system power consumption is increasing; secondly, the deepening of the pipeline makes the delay of the flip-flop account for an increasing proportion of the system clock cycle...

AI Technical Summary

Problems solved by technology

However, this flip-flop does not solve the power consumption problem caused by the keeper and the always-on inverter chain mentioned above, so its power consumption is still high when the flip-flop probability of the input D is high. to be higher than the HLFF flip-flop

[0004] To sum up, the existing flip-flops either consume a lot of power or have poor soft-edge characteristics

Images