4results about How to "Raise the voltage difference" patented technology

A surge protection circuit and an electronic device, the surge protection circuit comprising a first signal line, a second signal line, a first overvoltage protection module, a second overvoltage protection module, a third overvoltage protection module and a first voltage divider module. The first overvoltage protection module can take the voltage of the signal ground as a reference, release the surge current on the first signal line and the second signal line to the signal ground, limit the upper limit of the voltage of the first signal line and the second signal line, and the second overvoltage protection module and the third overvoltage protection module can avoid the voltage difference between the first signal line and the second signal line being too large, and further release the differential mode surge current on the first signal line and the second signal line. The first voltage divider module is arranged between the second overvoltage protection module and the third overvoltage protection module, which can avoid the excessively high voltage between the two ends of the second overvoltage protection module from affecting the protected module.

The invention discloses a method for realizing effective release of ferroelectric charges based on bit line segmentation and a storage array, and the method comprises the steps: segmenting a column address through a transmission gate, dividing a bit line into at least two bit line segments, and when data reading is carried out on a storage unit far away from a global amplifier, carrying out data reading on the storage unit; the read memory cell is disconnected from the memory cell close to one side of the global amplifier by using the transmission gate, and the bit line is shortened, so that the parasitic capacitance of the bit line is also reduced, the voltage difference between two ferroelectric capacitors can be increased, and the data reading accuracy is further improved.

The present disclosure provides a method, device and electronic device for detecting a storage array fault. The method includes: writing a first voltage and a second voltage to storage cells connected to a plurality of first bit lines and storage cells connected to a plurality of second bit lines in a storage array to be tested, respectively, wherein the first bit line and the second bit line are arranged adjacent to each other in an alternating manner, and the first voltage is greater than the second voltage; sequentially controlling a plurality of word lines to be turned on to read the storage cells, wherein controlling a plurality of word lines to be turned on includes controlling each word line to be turned on for a preset time, and then controlling a sensing amplifier connected to the first bit line or the second bit line to be turned on to read the storage cells, wherein the preset time is greater than the standard sensing delay time corresponding to the sensing amplifier; when the reading result of the storage cell is not equal to the first voltage or the second voltage written therein, it is determined that there is leakage of a coaxial word line dual-bit capacitor in the storage array to be tested. The embodiment of the present disclosure can quickly detect leakage between adjacent storage cells (coaxial word line dual bits) connected to the same word line.

This application provides a driving circuit, a driving chip, and a motor driving device. The driving circuit includes a full-bridge unit, a switching unit, and a driving unit. The first terminal of the switching unit is electrically connected to a first power supply, the second terminal of the switching unit is electrically connected to the first terminal of a first energy storage unit, and the third terminal of the switching unit is electrically connected to the power supply terminal of the driving unit and the first terminal of the second energy storage unit. The source of the target upper transistor in the full-bridge unit is electrically connected to the second terminal of the first energy storage unit. The second terminal of the second energy storage unit and the drains of all upper transistors in the full-bridge unit are electrically connected to the second power supply. The sources of all upper transistors and the drains of all lower transistors in the full-bridge unit are correspondingly electrically connected, and the sources of all lower transistors in the full-bridge unit are grounded. Multiple signal output terminals of the driving unit are correspondingly electrically connected to the control terminal of the switching unit, the gates of all upper transistors and the gates of all lower transistors in the full-bridge unit, which can solve the problem of high on-resistance of the upper transistors in the full-bridge circuit.