73results about How to "Raise the voltage difference" patented technology

An apparatus and method for stimulating animal tissue (for example to trigger a nerve action potential (NAP) signal in a human patient) by application of both electrical and optical signals for treatment and diagnosis purposes. The application of an electrical signal before or simultaneously to the application of a NAP-triggering optical signal allows the use of a lower amount of optical power or energy than would otherwise be needed if an optical signal alone was used for the same purpose and effectiveness. The application of the electrical signal may precondition the nerve tissue such that a lower-power optical signal can be used to trigger the desired NAP, which otherwise would take a higher-power optical signal were the electric signal not applied. Some embodiments include an implanted nerve interface having a plurality of closely spaced electrodes placed transversely and/or longitudinally to the nerve and a plurality of optical emitters.

An apparatus and method for stimulating animal tissue (for example to trigger a nerve action potential (NAP) signal in a human patient) by application of both electrical and optical signals for treatment and diagnosis purposes. The application of an electrical signal before or simultaneously to the application of a NAP-triggering optical signal allows the use of a lower amount of optical power or energy than would otherwise be needed if an optical signal alone was used for the same purpose and effectiveness. The application of the electrical signal may precondition the nerve tissue such that a lower-power optical signal can be used to trigger the desired NAP, which otherwise would take a higher-power optical signal were the electric signal not applied. Some embodiments include an implanted nerve interface having a plurality of closely spaced electrodes placed transversely and/or longitudinally to the nerve and a plurality of optical emitters.

There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.

The present invention provides a flash memory device and a method used for controlling erasing operation of the flash memory device.A non-volatile memory mechanism includes a first and a second memory cell blocks, wherein each memory cell block includes a plurality of memory cells, a local drain selection wire, a local source pole selection wire and a plurality of local character wires.A block selection unit respectively connects the set local character wires and an integral character wire to respond to block selective signals.A first voltage bias generator is allocated to be used for applying at least a first and a second erasing voltages which are positive ones to the integral character wire during the erasing manipulation period, wherein, the first erasing voltage is applied to the integral character wire during a first erasing try period of the erasing operation, the second erasing voltage is applied to the integral character wire during the second erasing try period, and a second erasing try is executed if a first erasing try does not make good erasing manipulation.A body voltage generator applies a body electric voltage to a body of the memory cell during the erasing manipulation period.

The invention provides a liquid crystal display panel, a liquid crystal display and a method for driving the same. The liquid crystal display panel comprises a data wire, a first scanning beam, a second scanning beam and a pixel, wherein, the second scanning beam is the next scanning beam adjacent to the first scanning beam; the pixel comprises a first sub-pixel, a second sub-pixel, a third switch, an auxiliary capacitor and a feedback capacitor; moreover, the first sub-pixel and the second sub-pixel are respectively comprise a first switch and a second switch; input ends of the first switch and the second switch are coupled with the data wire, controlled ends of the first switch and the second switch are coupled with the first scanning beam; and an output end of the third switch is coupled with a common electrode through the auxiliary capacitor and is coupled with an output end of the first switch through the feedback capacitor.

The invention discloses an LC bipolar resonant-based Cells-to-Cells equalization circuit and a control method thereof. During the equalization process, a microcontroller outputs four paths of rectangular wave driving signal of which frequencies are half of an LC resonant frequency, the phase difference is 90 degree and the duty ratio is 25% so that an equalization source unit and an equalization target unit are bipolarly and circularly connected to an LC resonant branch by a switch network, the LC resonant branch circularly works in states of positive polarity charging, positive polarity discharging, reverse polarity charging and reverse polarity discharging, and zero-current switch equalization of which energy is transmitted from the source unit to the equalization target unit is achieved. By the equalization circuit, equivalent release of a residual voltage of a resonant capacity C during the equalization process is achieved, the equalization source unit and the equalization target unit both can be adjacent arbitrary sections of Cells, the equalization circuit has the advantages of high power density, high equalization efficiency and control flexibility, and modular manufacturingis easy.

A low power system is disclosed for working in conjunction with a digital circuit that is disposed between positive and negative terminals. The system includes an internal voltage generator for increasing, for at least a first portion of the digital circuit, a voltage difference between the at least a first portion of the digital circuit and the voltage on at least one of the positive and negative terminals during a low power mode of operation. This allows the voltage across the at least first portion of the digital circuit to be less than the full voltage across the positive and negative terminals.

The invention discloses a dual-pole-dual-pole detecting method of mine working surface bottom plate terrane, which arranges the power electrodes A and B into one channel, while their midpoint is 01; powers the AB and measure the current I between AB; arranges the measuring electrodes M and N in another channel while their midpoint is 02; measures the voltage ªñU between them; and fixes AB to keep the MN length; moves MN distantly; therefore, the connecting line of 01 and 02 can scan a certain area to form a sector; keeps the AB length to move it to another position and repeat the operation; therefore, said connecting line can scan a certain area to form another sector; moves to the whole channel to complete the measurement. According to measured data, the invention uses resistance CT method to reversely calculate and process image treatment to accurately set the water content and structure of working surface bottom plate terrance. The invention has the advantages as strong detecting signal, less safe hidden, and high detecting accuracy.

A method and apparatus for gray level dynamic switching. The method is applied to driving a display with at least one pixel. In the method of the present invention, a gray level sequence S_G is provided. S_G sequentially represents two or more desired gray levels G_o(1), . . . , G_o(T) of the pixel at consecutive time frames 1, . . . , T and comprises a current gray level G_o(t) and a previous gray level G_o(t−1) corresponding to time frames t and t−1, respectively. Then, the pixel is driven with an optimized driving force V_d(t) to change the pixel forward to a state corresponding to G_o(t) according to G_o(t) and G_o(t−1). In the present invention, the optimized driving voltage V_d(t) is determined by equations of V_d(t)=V_o(t−1)+ODV and V_d(t)=a×G_d(m)³+b×G_d(m)²+c×G_d(m)+d, wherein the voltage ODV is a minimum voltage capable of obtaining one gray level transition in a determined response time.

The invention provides a split gate flash memory and a forming method thereof. The forming method of the split gate flash memory includes that: a first media layer and a floating gate layer are sequentially formed on a substrate; a discrete second media layer is formed on the floating gate layer, and an area where the second media layer is located is a word line area; first side walls are formed around the second media layer, and areas between adjacent first side walls are source electrode line areas; the floating gate layer and the first media layer are etched to the substrate by using the first side walls as masks; source electrode lines are formed on the source electrode line areas; a floating gate and a floating gate media layer are formed by removing the second media layer, and the floating gate layer and the first media layer under the second media layer; a third media layer is formed on a floating gate side wall below the top tip of the floating gate which is adjacent to the word line area; a tunneling media layer is formed to cover the substrate, the third media layer, the floating gate, the first side walls and the surfaces of the source electrode lines; and word lines are formed on the tunneling media layer of the word line area. By using the forming method, erasure performance is improved, voltage applied on the word lines is reduced, and power consumption is saved.

The invention discloses a hardening method for an inner surface of a cylinder barrel of a titanium and titanium alloy hydraulic cylinder. The hardening method comprises the following steps: I, polishing the inner surface of the cylinder barrel of the hydraulic cylinder, then, removing greasy dirt and dehydrating; II, putting the dehydrated cylinder barrel, which is used as a cathode, of the hydraulic cylinder in a double-layer glow ion diffusion metalizing furnace, putting a graphite source electrode in the cylinder barrel of the hydraulic cylinder, in the presence of argon gas, generating glow under the high-voltage electric fields by utilizing an anode and a cathode to perform bombardment activation on the inner surface of the cylinder barrel of the hydraulic cylinder; III, after the bombardment activation is finished, introducing a gas mixture of the argon gas and oxygen gas into the double-layer glow ion diffusion metalizing furnace, generating double-layer glow under the high-voltage electric fields by utilizing the anode and the graphite source electrode as well as the anode and the cathode to perform oxyarburizing on the inner surface of the cylinder barrel of the hydraulic cylinder to obtain a composite membrane layer on the inner surface of the cylinder barrel of the hydraulic cylinder. The composite film layer prepared by the hardening method disclosed by the invention is high in bonding strength and good in wear resistance, and capable of effectively avoiding the titanium and titanium alloy occlusive locking problem.

A voltage-enhanced-feedback sense amplifier of a resistive memory is configured to sense a first bit line and a second bit line. The voltage-enhanced-feedback sense amplifier includes a voltage sense amplifier and a voltage-enhanced-feedback pre-amplifier. The voltage-enhanced-feedback pre-amplifier is electrically connected to the voltage sense amplifier. A first bit-line amplifying module receives a voltage level of the second input node to suppress a voltage drop of the first bit line and amplifies a voltage level of the first input node according to a voltage level of the first bit line. A second bit-line amplifying module receives the voltage level of the first input node to suppress a voltage drop of the second bit line and amplifies the voltage level of the second input node according to a voltage level of the second bit line. A margin enhanced voltage difference is greater than a read voltage difference.

In order to improve the reading stability of a sensitive amplifier, the invention provides a reading auxiliary circuit method for improving the reading stability of the sensitive amplifier and the sensitive amplifier. Wherein the reading auxiliary circuit comprises an NMOS tube N6, the source end of the NMOS tube N6 is connected with negative voltage VNWL, the gate end of the NMOS tube N6 is connected with a control signal NSET2, and the drain end of the NMOS tube N6 is used for being connected with the drain end of a low-voltage pull-down tube N2 in the sensitive amplifier. In the CSL pulse period, firstly, the NOMS tube N2 is turned off, and the NMOS tube N6 is turned on, so that the NCS and the BL _ N are charged to a negative voltage VNWL; then, an NMOS tube N4 connected with the SAP1Tin the sensitive amplifier is opened; According to the invention, the NMOS tube N5 connected with the SAP2T in the sensitive amplifier is turned off, so that the PCS and the BL are charged to the VOD, the voltage difference between the BL and the BL _ N is further increased, and the capacity of the sensitive amplifier for resisting the coupling effect is improved.

The invention relates to a storage unit and a storage array erasing method. The storage unit comprises a P-type well region, a drain electrode, a source electrode, a first control grid electrode, a second control grid electrode and a middle electrode; the storage array erasing method comprises the following steps: applying first bias voltage to the P-type well region; applying second bias voltage to the drain electrode; applying third bias voltage to the source electrode; applying minus 6V-minus 8V voltage to the first control grid electrode; applying minus 6V-minus 8V voltage to the second control grid electrode; and applying 8V-9V voltage to the middle electrode, wherein the value of the first bias voltage is negative, and the values of the first bias voltage, the second first bias voltage and the third first bias voltage are equal. The storage unit and the storage array erasing method can improve the durability of the storage unit.

The invention relates to the technical field of an integrated circuit, and discloses a positive high-voltage charge pump. The charge pump comprises a charge pump circuit which is connected in multi-level series and a one-level output circuit; and the input end of the output circuit is connected with the output end of the last level charge pump circuit. According to the charge pump provided by the invention, an auxiliary circuit is added to reduce the PMOS (P-channel Metal Oxide Semiconductor) grid voltage in the charge pump circuit and increase the voltage difference of the grid electrode and the source electrode, thus, the PMOS grid voltage can be zero when the switch is switched on, and the voltage loss can be reduced during switching on and the PMOS conductive performance can be improved, thereby enhancing the capability of switch pumping charge.

The invention discloses a displayer and a pixel driving method. The displayer comprises a pixel driving circuit which comprises a first switch element, a second switch element, a third switch element and a fourth switch element, the first switch element has a first end, a second end coupled to a first node and a light-emitting element, and a control end coupled to a second node, the second switch element has a first end coupled to a first signal source, a second end coupled to the first end of the first switch element, and a control end coupled to a first scanning signal line, the third switch element has a first end coupled to a second signal source, a second end coupled to the second node, and a control end coupled to a second scanning signal line, and the fourth switch element has a first end coupled to a third node, a second end coupled to a grounding end, and a control end coupled to the second scanning signal line.

The embodiment of the invention provides a display substrate and a display device, the display substrate comprises a substrate and a fingerprint identification unit arranged on the substrate, and thefingerprint identification unit comprises an excitation circuit and a reading circuit. The reading circuit is configured to form a first capacitor with a fingerprint to be identified and read a chargequantity signal of the first capacitor, and the excitation circuit comprises a first thin film transistor and a first electrode plate connected with the first thin film transistor. the first thin film transistor is configured to apply a driving voltage to the first electrode plate, and the first electrode plate is configured to boost the voltage of the fingerprint to be identified through the driving voltage; and the fingerprint identification effect is improved.

A module comprises a bus invert encoder (24) for determining whether a set of data bits should be inverted prior to transmission over a communication bus. The bus invert encoder (24) produces a bus invert signal BI which controls a selective inversion means (28), for example a multiplexer. A partial fault detection encoder (32) determines one or more temporary check bits from the set of data bits, substantially in parallel with the bus invert encoder (24). Thus, the one or more temporary check bits are determined based on the assumption that the set of data bits are to be transmitted without inversion from the selective inversion means (28). A logic unit (34) is provided for correcting the one or more temporary check bits, if necessary, based on the bus invert signal produced by the bus invert encoder (24). The module has the e advantage of enabling the temporary check bits to be determined in parallel with the bus invert encoding, thereby reducing latency, with the logic unit being used to correct the check bits, if necessary, prior to transmission over the communication bus.