Read auxiliary circuit and method for improving read stability of sense amplifier in DRAM and sense amplifier

Abstract

In order to improve the reading stability of a sensitive amplifier, the invention provides a reading auxiliary circuit method for improving the reading stability of the sensitive amplifier and the sensitive amplifier. Wherein the reading auxiliary circuit comprises an NMOS tube N6, the source end of the NMOS tube N6 is connected with negative voltage VNWL, the gate end of the NMOS tube N6 is connected with a control signal NSET2, and the drain end of the NMOS tube N6 is used for being connected with the drain end of a low-voltage pull-down tube N2 in the sensitive amplifier. In the CSL pulse period, firstly, the NOMS tube N2 is turned off, and the NMOS tube N6 is turned on, so that the NCS and the BL _ N are charged to a negative voltage VNWL; then, an NMOS tube N4 connected with the SAP1Tin the sensitive amplifier is opened; According to the invention, the NMOS tube N5 connected with the SAP2T in the sensitive amplifier is turned off, so that the PCS and the BL are charged to the VOD, the voltage difference between the BL and the BL _ N is further increased, and the capacity of the sensitive amplifier for resisting the coupling effect is improved.

Description

technical field [0001] The invention belongs to the technical field of memory, and relates to a reading auxiliary circuit and a method for improving the reading stability of a sense amplifier in a DRAM and a sense amplifier using the reading auxiliary circuit. Background technique [0002] Such as figure 1 , 2 As shown in , 3, when the traditional sense amplifier is in the ACTIVE (activated) state, when SAP1T is low, SAP2T becomes high voltage, at this time N4 is closed, N5 is turned on, PCS remains at VBLH, thus the high voltage bit line also remains at VBLH. [0003] NSET is high, NCS is pulled down to ground so that the low voltage bit line remains at ground. [0004] When the DRAM reads, CSL becomes high, and N2 and N3 are turned on. On the one hand, due to the capacitive coupling between CSL and the bit line, the voltage of the low-voltage bit line will increase. On the other hand, because MDQ / MDQ_N is read before It is pre-charged to VINT, so when N2 and N3 are tur...

AI Technical Summary

Problems solved by technology

If VCSL is too high, the capacitive coupling effect and the charge sharing effect will be enhanced, and in severe cases, the sense amplifier will be flipped and the value of the memory cell will be changed.

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