Memory devices having bit line precharge circuits and associated bit line precharge methods

Abstract

A memory device having an off-current (Ioff) robust precharge control circuit and a bit line precharge method are provided. The precharge control circuit may be embodied as a delay circuit unit which receives and delays a precharge enable signal for a predetermined delay time; a NAND gate which receives the precharge enable signal and the output of the delay circuit; and an inverter which inverts the output of the NAND gate. The precharge control circuit may enable the word lines before disabling the precharge signal.

Description

[0001] Related literature [0002] This application claims priority under 35 U.S.C § 119 to Korean Patent Application No. 2003-36748 filed on June 9, 2003, the entire disclosure of which is incorporated herein by reference. field of invention [0003] The present invention relates to a semiconductor storage device, in particular to a semiconductor storage device with a bit line precharging circuit and a related bit line precharging method. Background of the invention [0004] With the advancement of semiconductor storage process technology, smaller and smaller semiconductor storage devices appear. Deep submicron processes are now being developed to facilitate the production of small, highly integrated memory devices. In order to improve the performance of developed transistors using deep sub-micron technology, this reduces the threshold voltage (Vth) of the transistor. However, when the threshold voltage is lowered, it increases the saturation current of the transistor in ...

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Problems solved by technology

Therefore, the cut-off current may reduce the operating speed of the memory device

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