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An element selection unit and a method therein

A technology for selecting units and elements, applied in the direction of architecture with multiple processing units, electrical components, separation devices of transmission paths, etc., to achieve the effects of low cost, improved performance, and low configuration overhead

Active Publication Date: 2015-07-01
TELEFON AB LM ERICSSON (PUBL)
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Further, shuffling circuits are expensive circuits because the number of two-input multiplexers included in a shuffling circuit scales quadratically with the number P of data elements as (P-1)*P

Method used

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  • An element selection unit and a method therein
  • An element selection unit and a method therein
  • An element selection unit and a method therein

Examples

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Embodiment Construction

[0044] Examples will be illustrated in the following non-limiting description.

[0045] Embodiments herein relate to high-throughput low-cost element selection units. The element selection unit is capable of selecting data elements from the input vector, concatenating the selected data elements, giving the selected set of data elements a common rotation, and merging the selected set of data elements with the output vector.

[0046] The selection of data elements from the input vector is based on a selection bitmap, ie, a vector of Boolean values.

[0047] Each data element corresponds to a word, a fixed size of W bits, which is handled as a unit. The word size may be equal to 8, 16 or 32 bits, for example.

[0048] The element selection unit includes P-1 two-input multiplexers ( 2 log(P)+1) layers, where the multiplexers are controlled individually, see Figure 6 , which will be described in more detail below. P is the number of data elements in the input vector and may b...

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PUM

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Abstract

An element selection unit (200) and a method therein for vector element selection. The element selection unit comprises a selector control circuit (404) and a selector data path circuit (406), which data path circuit comprises a plurality of layers of multiplexers. The element selection unit further comprises a receiving circuit (401) configured to receive an instruction to perform a selection of elements from an input vector. The selector control circuit (404) is configured to generate a multiplexer control signal for each multiplexer based on a bit map and on a plurality of relative offset values. The data path circuit is configured to propagate the elements comprised in the input vector through the plurality of layers of multiplexers towards an output vector based on the generated multiplexer control signals. The data path circuit is further configured to write the propagated elements to enabled elements of the output vector.

Description

technical field [0001] Embodiments herein relate to element selection for vector element selection and methods therein. Further embodiments relate to load store units including element selection units, memory-to-memory transfer systems including element selection units, vector processors including element selection units, and integrated circuits including vector processors. Background technique [0002] For some digital signal processing algorithms, input data must be gathered or organized before computation can begin. For example, when selecting a scatter set of data elements from a linear input vector, the selected data elements may be aggregated into a new linear output vector of subsequent data elements before computation can begin. This type of data aggregation or organization is required, for example, in the equalization process of data subcarriers in 3GPP Long Term Evolution (LTE) communication systems. LTE is a wireless communication standard that uses Orthogonal F...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/30G06F15/80
CPCH04L27/2649G06F9/30032G06F9/30036H04L5/0001G06F15/8076
Inventor D.范坎彭
Owner TELEFON AB LM ERICSSON (PUBL)
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