43 results about "Associative processor" patented technology

The present disclosure provides a search engine optimization (SEO) system comprising a remote server. The remote server comprises a memory with a set of executable routines and a search engine database with multiple fields of applications, each associated with multiple URLs indexed with a user engagement matrix, written data, and a search engine ranking. A processor acquires a web link from a computing device, extracts textual content, analyzes relevancy, and retrieves relevant URLs. The processor evaluates a thematic score, a readability score, and an emotional tone data using NLP techniques, analyzes written data of each URL to determine a topic weight, a legibility weight, and a sentiment tone data, develops a machine learning model, applies the model to recommend content alterations, and renders the alterations at the computing device.

In methods and systems for generating secure verification documents are disclosed, a processor that is associated with a multifunction print device will receive one or more source electronic document files, each of which includes content of one or more source documents, each associated with a unique content creator. The processor will cause a print engine of a multifunction device to print a plurality of verification document sheets, each of which comprises data from at least one of the source documents and includes a unique identifier (ID). After printing each verification document sheet, the processor will cause a scanner of the multifunction device to scan the verification document sheet to capture a digital image of the verification document sheet. The processor will then save the digital images of the verification document sheets to a data store.

A unit for accumulating multiplied bit values includes an array of bit-line processors. The unit is implemented in an in-memory associative processor, and each bit-line processor includes multiple memory cells coupled to a bit-line. The array of processors is arranged in rows and columns. The array passes bits of a first multiplicand vertically down a column and provides bits of a second multiplicand horizontally across a row. The array generates carry bits and passes them vertically to a subsequent processor in the same column. The array also generates sum bits and passes them diagonally to a subsequent processor in an adjacent column. The array includes multiplying processors, summing processors, and accumulator processors. Multiplying processors perform an XOR operation by simultaneously activating two memory cells and then perform a full adder operation. Summing processors perform a full adder operation. Accumulator processors perform a full adder operation that includes a feedback sum bit from a previous cycle.

A flux sensing system includes a processor, a memory, and a sensor. The memory stores at least one semantic profile having a first preference setting, a second preference setting, and a third preference setting in which the first preference setting is associated with a first object, the second preference setting is associated with a second object and the third preference setting is associated with a semantic group including the first object and the second object. The processor infers a semantic associated with a third object, the inferred semantic being based on one or more inputs from the sensor. The processor further detects the presence of the first object and the second object based on inputs from the sensor, and applies or does not apply preference settings based on detected object presence and inferences of the semantic group.

An electronic gaming system including a memory and a processor is described. The processor is configured to cause a persistent feature to be provided as being associated with an electronic game and a player account. The processor is also configured to, as play of the electronic game by the player account progresses, cause a meter associated with the persistent feature to fill, wherein as the meter fills, return to player (RTP) of the electronic game increases, and wherein the meter is caused to be filled based upon a bonus symbol being provided during play of the electronic game. The processor is further configured to, after a predetermined amount of time passes where no plays of the electronic game by the player account occur, cause the meter associated with the persistent feature to empty, wherein as the meter empties, RTP of the electronic game decreases.

The invention relates to a system and method for selecting assignments for components of a computer-aided device. A device management system may include a device including a drive assembly configured to be removably coupled with an instrument. The drive assembly may include a plurality of drive elements configured to cause movement of the instrument by driving a plurality of input elements of the instrument. The control system may include a processor configured to select a first assignment from a plurality of assignments for a first drive element of the plurality of drive elements, the first assignment being available for at least two drive elements of the plurality of drive elements. The first assignment may be associated with a first pair of the first drive element and a first input element of the plurality of input elements. The processor may be configured to cause the first drive element to employ the first assignment.

A wireless communication device includes one or more antenna arrays that receives RF signals across a plurality of frequency bands. The wireless communication device applies band-specific filtering operation to the received RF signals to obtain filtered RF signals. The wireless communication device converts and digitizes the filtered RF signals to obtain digitized intermediate frequency (IF) signals. The wireless communication device executes a plurality of spectrum measurements for the digitized IF signals. Each spectrum measurement of the plurality of spectrum measurements is based on a different offset frequency of a sequence of offset frequencies. Each spectrum measurement is associated with a first frequency resolution. The processor stores phase coherence information for each spectrum measurement. The processor combines the plurality of spectrum measurements based on the stored phase coherence information to generate a spectrum analysis output with a second frequency resolution that exceeds the first frequency resolution.

Exemplary systems and methods are directed to a dynamic flight exchange configured for re-selling charter flight assets through plural provider dashboards. A user interface receives a user interface including plural parameters that correspond to the first interactive display of one of the plural provider dashboards. The plural parameters being associated with one of the sale or the purchase of a target charter flight asset. The processor can initiate an exchange event including one of a query or an online an online auction for the target charter flight asset associated with user input. The processor receives data from the server in response to the user input and generates a second interactive having an arrangement of data based on results of the exchange event. The user interface receives a user response to the arrangement of data and the processor controls the exchange event on the network based on the user response.

To provide a system and a method for a hardware partition of a cloud server.SOLUTION: The system includes one or more processor cores including a managed processor core that executes instructions to divide at least a portion of the one or more processor cores into one or more partitions, and at least one distributed virtual memory (DVM) hub that obtains DVM messages from the processor cores, determines one or more recipient processor cores of the DVM messages, and provides the DVM messages to the determined recipient processor cores. The system also includes one or more interrupt interposers that are each associated with a processor core and that prevent interrupts originating from the associated processor core from being provided to processor cores that are outside of the partition of the associated processor core.SELECTED DRAWING: Figure 1

The invention relates to one-to-many TCP connection splicing. A computing device includes at least one network interface controller (NIC), a memory, and at least one processor including one or more cores. The NIC (s) receive inbound transmission control protocol (TCP) data packets and transmit outbound TCP data packets. The memory stores a program of instructions that the processor executes to divide a data path within the computing device that includes both a receiving endpoint and a transmitting endpoint into a first path and a second path. In response to determining that the first inbound TCP data packet is associated with the established TCP connection and the data stitching group, the processor assigns the first inbound TCP data packet to the first path and assigns a second inbound TCP data packet that is not assigned to the first path to the second path. The processor performs a one-to-many data stitching of payload data from the first inbound TCP data packet to the outbound TCP data packet using the first path.

A flux sensing system includes a processor, a memory, and a sensor. The memory stores at least one semantic profile having a first preference setting, a second preference setting, and a third preference setting in which the first preference setting is associated with a first object, the second preference setting is associated with a second object and the third preference setting is associated with a semantic group including the first object and the second object. The processor infers a semantic associated with a third object, the inferred semantic being based on one or more inputs from the sensor. The processor further detects the presence of the first object and the second object based on inputs from the sensor, and applies or does not apply preference settings based on detected object presence and inferences of the semantic group.

A system comprises one or more processor cores, including a management processor core that executes instructions to partition at least a portion of the one or more processor cores into one or more partitions. The system includes at least one distributed virtual memory (DVM) hub that obtains a first DVM message from a processor core; determines, based on a processor core identifier of the DVM message, one or more recipient processor cores for the first DVM message; and provides the first DVM message to the one or more recipient processor cores. The system includes one or more interrupt interposers that are each associated with a processor core and prevent an interrupt originating from the associated processor core from being provided to a processor core that is outside the partition of the associated processor core.

Apparatuses, methods, and systems are disclosed for scheduling a sidelink transmission. One apparatus includes a processor and a transceiver that receives a TB on SL resources, where the TB is associated with a SL HARQ process. The processor stores the TB in a HARQ soft buffer and makes available the HARQ soft buffer for new data in response to a predefined trigger.

An apparatus includes a processor operatively coupled to a memory. The processor detects a software application installed on a client computing device, and / or usage data. Detected usage data is associated with a current user of the client computing device and with the software application. The processor identifies a user role for the current user based on the software application and / or usage data. The processor applies a security configuration to the client computing device based on the user role. The security configuration limits access by the current user to a portion of the software application. The processor sends an identifier of the user role to an administrative server for storage in an Active Directory (AD) database.

The invention provides a heterogeneous computing system and method, electronic equipment and a storage medium. The system comprises a high-performance processor core which issues an instruction stream to an associated processor core through a network-on-chip; the instruction stream comprises a vector instruction and a scalar instruction corresponding to the vector instruction; the associated processor core comprises a control core, a vector control unit and a calculation storage unit; the control core executes the scalar instruction, and when the vector instruction is recognized, the vector instruction is forwarded to the vector control unit; the vector control unit translates the vector instruction into a storage operation primitive; and the computing storage unit executes in-memory computing based on the storage operation primitive, and returns a computing result to the high-performance processor core through the network-on-chip. In the system, the high-performance processor core focuses on the complicated control logic which the high-performance processor core is good at, and the data parallel part is unloaded to the associated processor core, so that the overall calculation efficiency of the workload is effectively improved by distributing different types of workloads to the corresponding processors for processing.

Methods and systems for enhancing data transfer security using artificial intelligence are described. In one aspect, a system or processor executes a method that includes receiving first data associated with a first data transfer. The processor may generate a first score by passing at least a portion of the first data to a scoring artificial intelligence model. The first score indicates a first priority. The first data transfer and the first score may be associated with a first pointer. The processor inserts the first pointer into a priority data structure. The processor detects a distribution trigger condition associated with an operating device. In response, the processor removes, A pointer from the priority data structure. The pointer is associated with a respective data transfer. The processor sends data associated with the respective data transfer an operating device.

The testing system comprises a processor and a local memory on a motherboard and an extension memory device under test (DUT). The local memory corresponds to a first address range within system memory and the extension memory DUT associated with a second address range within the system memory. The processor is operable to direct write latency testing of the extension memory DUT, including recording write latency measurement values. The recording can be done in a frequency table and the frequency table can be visualized (e.g., rendered, etc.) on a display. The testing comprises non-temporal write instructions that bypass processor caches. The extension memory DUT is compatible with a compute express link (CXL) protocol.

A computer-implemented method is provided. A processor set receives a dataset comprising a set of data and metadata associated with the set of data from a database. The processor set generates a number of outputs by inputting the set of data and the metadata to a computational model. The processor set associates the number of outputs to the dataset to generate a number of associations. The processor set creates a number of visualizations based on context from the number of associations using a graphical user interface. The processor set removes a subset of data from the set of data and a subset of metadata associated with the subset of data from the metadata based on the visualizations to generate an updated dataset. The processor set updates functions for the computational model based on the visualizations. The processor set generates updated outputs by inputting the updated dataset to the computational model.

The present disclosure relates to systems and method for generating a quantum random number using a quantum network. The system may comprise a receiver for receiving from a plurality of nodes in a quantum network a plurality of initial quantum random numbers "IQRNs", wherein each initial quantum random number (IQRN) is generated by executing a quantum protocol between a first node and a second node comprised in the quantum network, and wherein each IQRN is associated with a first unique identifier (ID) uniquely identifying the first node, and a second unique identifier (ID) uniquely identifying the second node; a processor configured to: analyse the plurality of IQRNs and retain a subset of the IQRNs that satisfy a consensus criterion; generate the QRN using the subset of retained IQRNs.

A wireless transceiver / receiver unit (WTRU) comprises a processor configured to receive configuration information. The configuration information may include a plurality of associated identification (ID) groups, one or more associated identifiers (IDs) associated with each associated ID group of the plurality of associated ID groups, and / or a plurality sets of radio resource control (RRC) configurations, where each set of RRC configurations is associated with an associated ID. The processor may be configured to receive indication that an associated ID group of the plurality of associated ID groups is associated with one or more cells, activate a first cell using a first set of RRC configurations of the plurality of sets of RRC configurations, receive an activation message to activate a second cell, and perform an activation procedure.

An item tracking system comprises a plurality of cameras, a memory storing associations between item identifiers of respective items, and a processor configured to capture a plurality of first images of a first item and identify a first item identifier of the first item based on the first images. The processor captures a plurality of second images of a second item, generates cropped image of the second item from each second image, and identifies an item identifier for each cropped image. Based on the associations stored in the memory, the processor determines that an association exists between the first item identifier of the first item and a second item identifier, and assigns the second item identifier to the second item when at least one of the item identifiers corresponding to the cropped images is the second item identifier.

A computer-implemented system for creation, matching, and trading of private-asset derivative instruments (synthetic or standard) for portfolio management and risk transfer is provided. The system include one or more databases organized into logical subdivisions associated with users of different qualifications, the databases storing digital identities representing private assets, private-asset derivative instruments and derivatives archetypes. Processors, which can be cloud-deployed, are configured to receive user preferences for risk, return, and exposure; determine user access rights; identify or create a derivatives archetype that satisfies those preferences; and generate or return a corresponding private-asset derivative instrument for portfolio management, risk transfer, or trading. Archetypes are associated through machine-readable references with digital identities of corresponding instruments or their underlyings. The processors may employ quantitative or machine-learning models to convert user preferences into statistical descriptors, select private-asset representatives, project cash flows, and match users on a trading platform for execution or restructuring of transactions.

To provide a system and a method for a hardware partition of a cloud server.SOLUTION: The processor executes an instruction to divide at least a portion of one or more processor cores included in the system for hardware partition into one or more partitions. The system includes each distributed virtual memory (DVM) interposer includes a partition identifier that identifies a partition. Each DVM interposer performs a proactive action in response to receiving a message with an identifier different from its own partition identifier. The system includes each interrupt interposer associated with a processor core of the one or more processor cores. Each interrupt interposer prevents interrupts originating from the associated processor core from being provided to processor cores outside of the partition of the associated processor core.SELECTED DRAWING: Figure 1

A system for invoice management related to wearable medical devices is disclosed. The system includes a processor and a memory including instructions, which when executed, cause the processor to receive a user creation input to create an invoice for tasks associated with a wearable medical device. The processor, additionally, displays invoice entry options based on the invoice type. The invoice entry options are associated with the tasks and / or expenses. Further, the processor receives selected invoice entries of the invoice entry option and determines, via a fee schedule, a fee for each of the one or more selected invoice entries. Furthermore, the processor generates the invoice including the selected invoice entries and the fee associated with the selected invoice entries.

A method for continuous glucose monitoring includes a processor of a computing device operatively coupled to or integrated with a display receiving data. The data includes a plurality of glucose levels, and each glucose level of the plurality of glucose levels is associated with a corresponding time. The processor processes the data to generate a first graphical element indicative of a current glucose level, and one or more second graphical elements indicative of a rate and a direction of change of the glucose level. The processor via a graphical user interface displays the first graphical element on the display and the one or more second graphical elements on the display. The one or more second graphical elements are positioned relative to the first graphical element to visually indicate whether the glucose level is stable, increasing, or decreasing.

A method for continuous glucose monitoring includes a processor of a computing device operatively coupled to or integrated with a display receiving data. The data includes a plurality of glucose levels, and each glucose level of the plurality of glucose levels is associated with a corresponding time. The processor processes the data to generate a first graphical element indicative of a current glucose level, and one or more second graphical elements indicative of a rate and a direction of change of the glucose level. The processor via a graphical user interface displays the first graphical element on the display and the one or more second graphical elements on the display. The one or more second graphical elements are positioned relative to the first graphical element to visually indicate whether the glucose level is stable, increasing, or decreasing.

Reduce the amount of work required to analyze cyber-attack methods. [Solution] An attack method analysis support device having a processor and memory, wherein the memory stores a protected asset, which is either a function of a system element constituting an information processing system, data processed by the function of the system element, or a function of software constituting the system element and data processed by the function of the software, in association with an attack method of a cyber attack against the protected asset, and the processor identifies the protected asset to be analyzed based on information received from a user via an input device, calculates the similarity between the protected asset to be analyzed and the protected asset stored in the memory, identifies an attack method against the protected asset to be analyzed from the attack methods associated with the protected assets stored in the memory based on the similarity, and outputs the identified attack method against the protected asset to be analyzed to an output device.

A numerical control device (10) controls a machine tool (1) to which a plurality of tools are detachably attached. The numerical control device (10) comprises at least one memory (30) and at least one processor (40). In the memory (30), identification information of a plurality of tool groups, in which a plurality of tools are classified on the basis of shape information relating to the shape of each tool and to each of which two or more tools belong, is stored, and also control information that is set for each tool and used to control the machine tool (1) is stored in association with the identification information of the tool group to which the corresponding tool belongs. The processor (40) acquires additional identification information added as identification information and additional control information added as control information, and compares the additional control information with control information of each tool belonging to the tool group having the same identification information as the additional identification information.

A device for transaction management includes a local memory configured to store a copy of blockchain records corresponding to blockchain records of a trusted entity, each of the blockchain records associated with a transaction corresponding to a commodity smart contract. A processor is configured to generate a transaction certificate to certify a transaction, the transaction certificate being in a form of a non-fungible token (NFT) that is recorded onto one of the blockchain records in the local memory associated with the transaction, provide the transaction certificate to one or more participants of the transaction, and submit the transaction certificate to the trusted entity for recordation onto the one of the blockchain records managed by the trusted entity associated with the transaction corresponding to the commodity smart contract when a network connection between the device and the trusted entity is available.

This disclosure provides systems, apparatus, devices, and methods for illumination-based relighting frameworks, including computer programs encoded on a storage medium. A processor computes a normal map based on a masked, gamma-corrected foreground image via an ML model. The processor computes a lightmap based on the normal map and an HDR map. The processor generates an image based on the lightmap, a first cropped image associated with the foreground image, and a second cropped image associated with the foreground image, wherein the first cropped image is associated with a first saturation level and the second cropped image is associated with a second saturation level less than the first saturation level. The processor outputs an indication of the generated image.