This application relates to the field of
semiconductor inspection technology, specifically to
semiconductor wafer inspection methods and systems. In application, this application achieves
fully automated execution of the entire process, including automated
probe calibration, automated vector network calibration, automated vision calibration, and automated teaching, ultimately enabling automated inspection of each
chip on the
wafer to be inspected. Through parameter configuration, multi-dimensional calibration, vision teaching, and automated inspection, the entire
wafer inspection process is automated. First,
chip and probe parameters are set, then probe horizontal calibration, vector network
system error calibration, and vision positioning calibration are performed sequentially. Next,
chip model features are created, and pin-punch teaching positions are marked to achieve automatic chip location, precise pin
punching, and power-on circuit detection. The entire execution process eliminates multi-dimensional errors such as probe posture,
signal transmission, and
spatial positioning, ensuring the authenticity and reliability of inspection data, improving the accuracy, efficiency, and consistency of wafer inspection, and adapting to the high-precision inspection needs of large-scale
semiconductor wafers.