33 results about "Logic modeling" patented technology

A delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I / O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow. Physical design of the solidified drive and receive logic blocks permits simple fit within ASIC place and route flows for increased ease of implementation and ease of reuse.

The present invention provides a failure logic modeling method for a high-speed railway train operation control on-board system, including the following steps: determining the functional relationship between the structure and the parts of the train control on-board system; analyzing the failures of the parts based on known failures of the train control on-board system in combination with brainstorming; establishing an FMEA table to generalize the failures of the parts; editing and simulating the failures by using a modeling tool. By adopting the present invention, the failure modes analyzed are more systematic, and the failure logic modeling can be carried out from a global perspective more easily, the whole process can be better targeted meanwhile, the security analysis complexity of the train control system will be effectively reduced and the development period of the train control system will be shortened.

A formal verification method for the design and implementation of wireless sensor network security protocols, including the following steps: (1) Design method of sensor network security protocols based on logic analysis: the sensor network security protocol designer accepts a protocol design goal, in On the basis of analyzing the environmental factors of the sensor network, design a prototype of the protocol; establish a logical reasoning system, complete the protocol modeling and logical analysis, modify the protocol design plan according to the analysis results, repeat the logical analysis until the protocol logic is correct; finally give the protocol specification (2) A security protocol specification description language for the sensor network development environment; (3) An automatic verification method for security protocol codes based on model checking. The invention effectively guarantees the safety and efficiency of design and development, and has good expandability.

A method for providing a voice application includes executing control flow logic modeling a dialog flow with a user via a voice browser. The control flow logic produces a disambiguation requirement. A disambiguation module is initiated and a set of at least two candidates and partitioning criteria is sent from the control flow logic to the module. Attributes of the candidates are analyzed to determine a partitioning score for each attribute indicative of ability to distinguish between candidates based on the partitioning criteria. The attributes are sorted based on the partitioning scores. The user is queried based on a top-sorted attribute and results of the query are used to reduce the set of candidates. The steps of analyzing, sorting, and querying are repeated until the set of candidates is reduced to a single candidate. The single candidate is returned to the control flow logic for continued execution.

The invention discloses an equipment modeling language based embedded type emulated serial port and a modeling method thereof. Functional logic sends data to an exterior or sends external data to user interaction control logic or data processing control logic; the user interaction control logic obtains the external data, sends the external data to the data processing control logic, time sequence control logic or functional logic, receives the data sent by the functional logic or the data processing control logic and then displays the data; comprehensive processing logic and interface adapting logic realize data interaction of each logic; the data processing control logic performs format conversion for the data and then sends the processed data to the time sequence control logic, the user interaction control logic or the functional logic; and the time sequence control logic receives the data and sends the data to the functional logic according to a control time sequence. According to the equipment modeling language based embedded type emulated serial port and the modeling method thereof, as an embedded type hardware serial port is subjected to logic modeling and functional decomposition, the problem in the prior art that the logic level is lack of description for an embedded type hardware serial port simulation modeling method is solved.

The invention discloses a verification method for a simulation model of a power system, which provides a simulation model parameter record and a model rule verification process, and builds a cloud simulation model parameter library and a rule library to meet the requirements of multiple users, multiple terminals (including mobile phones, tablet computers), The operation logic verification requirements in the remote modeling process form a timely inspection of the simulation modeling, timely feedback process, and record the trajectory information of the simulation modeling at the same time, improve the simulation modeling process and improve the efficiency of the simulation modeling.