Clock domain crossing AHB (advanced high-performance bus) bridging method and device

Abstract

The invention discloses a clock domain crossing AHB (advanced high-performance bus) bridging method and device. The device comprises a master control logic module, a slave control logic module, a master clock and slave clock data latching module and an asynchronous pulse and synchronous circuit module. The master control logic module generates a bus control signal of a master clock domain according to a bus signal of a master device; the master control logic module generates a response signal fed back to the master device according to a slave device bus signal sampled in the master clock domain and latched by a slave clock domain; the slave control logic module generates a bus control signal of the slave clock domain according to a response signal of a slave device and a master device bus signal sampled in the slave clock domain and latched by the master clock domain; when the bus control signal is effectively enabled, the master clock and slave clock data latching module latches and samples synchronous data; the asynchronous pulse and synchronous circuit module synchronizes clock domain crossing signals to an opposite-party clock domain. The clock domain crossing AHB bridging method and device have the advantage that the master and slave devices can implement the AHB protocol under any frequency.

Description

technical field [0001] The invention relates to the technical field of AHB (Advanced High performance Bus, advanced high performance bus), in particular to a cross-clock domain AHB bus bridging method and device. Background technique [0002] With the increase of SOC (System on Chip, System on Chip) integrated circuit function complexity and the promotion of IP (Internet Protocol, Internet Protocol) multiplexing design, on-chip bus design has become a key issue. The AMBA (Advanced Microcontroller Bus Architecture, Advanced Microcontroller Bus Architecture) AHB bus introduced by ARM is widely used in data transmission. In the early chip design based on the AHB bus, both the master device and the slave device work in the same clock domain. In modern low-power design, multi-clock domain management is an effective way to reduce power consumption, so that different devices work on different clocks, such as low-frequency clock modules in a low-power state. However, when working ...

AI Technical Summary

Problems solved by technology

However, adding FIFO to prevent asynchronous data loss will increase the area cost and logic design complexity of the circuit

Images