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A time sequence repairing method based on time headroom

A repair method and timing technology, applied in the direction of instrumentation, calculation, electrical digital data processing, etc., can solve unreasonable problems, achieve the effect of reducing design area, increasing operating frequency, and optimizing line network delay

Active Publication Date: 2019-04-05
AMICRO SEMICON CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In order to solve the irrationality of the existing technology, the purpose of the present invention is to provide a method for judging how to solve the timing problem according to different slack values. The technical solution is as follows :

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  • A time sequence repairing method based on time headroom
  • A time sequence repairing method based on time headroom
  • A time sequence repairing method based on time headroom

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Embodiment Construction

[0023] The technical solutions in the embodiments of the present invention will be described in detail below with reference to the drawings in the embodiments of the present invention. It should be understood that the specific embodiments described below are only used to explain the present invention, not to limit the present invention.

[0024] The principle of the solution of the present invention is to implement corresponding processing methods according to different time margin slack, because when the absolute value of time margin slack exceeds a certain threshold, it is no longer possible to repair the timing by constraining the clock path, only by modifying The layout of the chip is to reduce the absolute value of the time margin slack, and then the timing is repaired by constraining the clock path. To this end, an embodiment of the present invention provides a timing repair method based on a time margin, such as figure 1 As shown, the detailed steps are as follows:

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Abstract

The invention provides a time sequence repairing method based on time headroom, which comprises the following steps: step 1, extracting netlist information of all paths in a chip layout, and then entering a step 2; Step 2, determining a time sequence violation path in the generated static time sequence analysis and a corresponding time margin based on the configured time sequence constraint condition, and then entering a step 3; Step 3, judging whether the time margin is greater than a preset threshold value or not, if so, determining a starting point or an end point of a preset analysis pathin the time sequence violation path, and adjusting the magnitude of the clock delay of the time sequence violation path; Otherwise, analyzing based on the static time sequence; The method comprises the following steps: firstly, extracting logic units on a data path and a clock path according to a preset time sequence violation path, further extracting logic modules connected with the time sequenceviolation path and line network information of the logic modules, adjusting the line length between the logic modules connected with the time sequence violation path, performing optimized layout according to the optimized line length, and then returning to the step 1. The design area of the chip is reduced, and the working frequency of the chip is improved.

Description

technical field [0001] The invention relates to the field of automatic wiring of integrated circuit layouts, in particular to a time sequence repair method based on time margin. Background technique [0002] In the design of integrated circuit chips, there are several main factors that determine the operating speed and design area of ​​integrated circuit chips: production technology, code writing style, physical implementation process from code to layout, etc. Fixing timing is one of the most important critical steps in the code-to-layout physical implementation process. In the traditional implementation method, the processing of timing repair is generally aimed at the data path, such as increasing the size of the device on the data path to increase its driving capability, or inserting a buffer at a node with a heavy fan-out burden to reduce each node. Fan-out burden and so on. No matter which of the above implementation methods will increase the area of ​​the chip, even i...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/392
Inventor 叶虎强黄明强
Owner AMICRO SEMICON CORP
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