10results about How to "Improve gate reliability" patented technology

The invention provides a quasi-super junction planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; performing epitaxial growth on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, performing ion implantation, forming a plurality of N-type body regions and a plurality of diffusion regions, and forming a P-type well region, an N-type source region and a current sharing layer; re-forming a barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer; a barrier layer is formed again, the barrier layer is etched to form a through hole, metal is deposited, and a gate metal layer is formed; the preparation method comprises the following steps of: re-forming a barrier layer, etching the barrier layer to form a through hole, depositing metal, forming a source metal layer, removing the barrier layer, and completing preparation, so that a quasi-super junction structure and a current sharing layer are constructed in the device, and the voltage endurance capability, the gate reliability and the conduction capability of the device can be effectively improved.

The invention provides a heterogeneous trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer above the drift layer, and performing etching and ion implantation to form a P-type well region, an N-type source region and a masking region; forming a barrier layer again, and etching and depositing the insulating medium to form a first insulating medium region; forming a barrier layer again, and etching to form a groove; forming a barrier layer again, etching and depositing metal, and forming a suspension gate; forming a barrier layer again, and etching and depositing the insulating medium to form a second insulating medium region; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer; the preparation method comprises the following steps: preparing a source electrode metal layer, re-forming a barrier layer, etching, depositing metal, forming a source electrode metal layer, removing the barrier layer, and completing the preparation, thereby realizing the characteristics of low switching loss, high switching speed and low on-resistance.

The invention provides a quasi-super junction trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; a barrier layer is formed above the drift layer, etching and ion implantation are carried out, a plurality of N-type regions, a plurality of P-type masking regions, a P-type well region, an N-type source region and a P-type source region are formed, the barrier layer is formed again, etching and oxidation are carried out to form a gate dielectric layer, and a groove is formed in the gate dielectric layer; and forming a barrier layer again, etching, depositing metal, forming a gate metal layer and a source metal layer, and removing the barrier layer to complete preparation. An N-type region and a masking region are constructed in the device, so that a transverse and longitudinal combined quasi super junction voltage-withstanding structure is formed to improve the voltage-withstanding capability of the device, and meanwhile, the N-type region can reduce the on resistance of the device.

This application provides a semiconductor structure and a method for forming the same. The semiconductor structure includes: a semiconductor substrate with a first insulating layer formed on its surface; a gate signal conditioning circuit and a virtual circuit disposed on the surface of the first insulating layer, wherein the gate signal conditioning circuit and the virtual circuit have identical structures; one end of the gate signal conditioning circuit is connected to a gate signal source, and the other end is connected to the gate of a device cell, wherein the gate signal conditioning circuit is used to adjust the resistance between the gate signal source and the gate of the device cell; one end of the virtual circuit is connected to a virtual gate monitoring signal terminal, and the other end is connected to a virtual gate monitoring ground terminal, wherein the virtual circuit is used to simulate the operation of the gate signal conditioning circuit and is monitored.

The utility model provides an asymmetric high-reliability trench gate silicon carbide VDMOS. The asymmetric high-reliability trench gate silicon carbide VDMOS is characterized in that a drift layer is connected to a silicon carbide substrate; the P-type well region is connected to the drift layer; the shunt region is connected to the drift layer and located at the lower left corner of the first groove, and the P-type base region is connected to the shunt region and located at the left side of the first groove; the P-type source region is connected to the P-type well region; the N-type source region is respectively connected with the P-type well region, the P-type base region and the P-type source region; the Schottky metal layer is connected to the drift layer, the P-type well region and the N-type source region; the outer side surface of the insulating dielectric layer is respectively connected with a P-type source region, an N-type source region, a P-type well region, a P-type base region and a shunt region; a groove is formed in the insulating medium layer; the gate metal layer is arranged in the groove; the source metal layer is respectively connected with the P-type source region, the N-type source region and the Schottky metal layer; the drain metal layer is connected to the silicon carbide substrate, so that the characteristics of the device after conduction are ensured at one side, the follow current characteristics of the diode of the device body are ensured at one side, and the reliability of the device is improved.

This application discloses a SiC MOSFET, a SiC MOSFET preparation method, and an integrated circuit. In the SiC MOSFET, a gate electrode is located on two sides of a fin-shaped channel layer. Disposing the gate electrode on the two sides of the fin-shaped channel layer is conducive to reducing a width of the fin-shaped channel layer. This is favorable for global inversion of the fin-shaped channel layer, thereby forming a large carrier path in the fin-shaped channel layer. In this way, most carriers in the SiC MOSFET flow through an electron path formed in the fin-shaped channel layer, so that a quantity of carriers that flow on an edge of a gate oxide layer is reduced, thereby greatly improving channel mobility and also improving reliability of the gate oxide layer.

The embodiment of the invention discloses a semiconductor device and a preparation method of the semiconductor device. The semiconductor device includes a substrate; the buffer layer is arranged on one side of the substrate; the channel layer is arranged on one side, far away from the substrate, of the buffer layer; the barrier layer is arranged on one side, far away from the substrate, of the channel layer; the cap layer is arranged on one side, far away from the substrate, of the barrier layer; the regulation and control layer is arranged on the side, away from the substrate, of the cap layer, the orthographic projection of the regulation and control layer on the substrate at least partially covers the orthographic projection of the cap layer on the substrate, and the regulation and control layer is used for regulating the uniformity of the electric field of the cap layer. According to the technical scheme provided by the embodiment, the uniformity of the electric field between the cap layer and the grid electrode is adjusted, so that the voltage endurance capability of the grid electrode is improved, and the reliability of the semiconductor device is improved.

The invention provides a drain-source voltage overshoot resistant silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; performing ion implantation on the drift layer to form a conductive layer; forming a barrier layer, etching, carrying out ion implantation, and forming a masking layer and a P-type well region; re-forming a barrier layer, etching, and then depositing to form an insulating medium layer and an N-type source region; a barrier layer is formed again, etching and ion implantation are carried out, and a P-type source region is formed; a barrier layer is formed again, a gate dielectric layer is formed through etching and oxidation, and a groove is formed in the gate dielectric layer; and forming a barrier layer again, etching, depositing metal, forming a gate metal layer and a source metal layer, and removing the barrier layer to complete preparation. And the switching speed is improved while the drain voltage impact resistance of the device is improved.

The invention provides a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a semiconductor substrate, an epitaxial layer is formed on the surface of the semiconductor substrate, and a contact doping region is formed in the epitaxial layer; the shielding doped regions are located in the epitaxial layer on the two sides of the contact doped region, and the doping type of the shielding doped regions is opposite to that of the contact doped region; the well region is located in the epitaxial layer at the bottom of the contact doped region, the doping type of the well region is opposite to that of the contact doped region, and the depth of the shielding doped region is larger than that of the well region and larger than that of the contact doped region; the trench gate structures are located on the two sides of the shielding doped region and penetrate through part of the shielding doped region to be connected with the well region and the contact doped region, and the depth of the trench gate structures is larger than that of the well region and smaller than that of the shielding doped region. The MOSFET unit structure can solve the problems that an existing MOSFET unit structure is not high in reliability and low in integration level.

The utility model provides a silicon carbide VDMOS capable of improving gate reliability. The silicon carbide VDMOS is characterized in that the lower side surface of a drift layer is connected to the upper side surface of a silicon carbide substrate; the lower side surface of the current-sharing layer is connected to the upper side surface of the drift layer, and the current-sharing layer is provided with a groove. The lower side surface of the well region is connected to the upper side surface of the current sharing layer; the lower side surface of the P-type source region is connected to the upper side surface of the well region; the lower side surface of the N-type source region is connected to the well region, and the outer side wall of the N-type source region is connected to the inner side wall of the P-type source region; the composite gate dielectric layer passes through the N-type source region and is connected to the groove; a groove is formed in the composite gate dielectric layer; the source electrode metal layer is respectively connected with the P-type source region and the N-type source region; the gate metal layer is arranged in the groove; the drain metal layer is connected to the lower side face of the silicon carbide substrate, the composite gate dielectric is adopted, the gate voltage can be effectively borne, and the gate reliability is improved.