3results about How to "Improve gate reliability" patented technology

This application provides a semiconductor structure and a method for forming the same. The semiconductor structure includes: a semiconductor substrate with a first insulating layer formed on its surface; a gate signal conditioning circuit and a virtual circuit disposed on the surface of the first insulating layer, wherein the gate signal conditioning circuit and the virtual circuit have identical structures; one end of the gate signal conditioning circuit is connected to a gate signal source, and the other end is connected to the gate of a device cell, wherein the gate signal conditioning circuit is used to adjust the resistance between the gate signal source and the gate of the device cell; one end of the virtual circuit is connected to a virtual gate monitoring signal terminal, and the other end is connected to a virtual gate monitoring ground terminal, wherein the virtual circuit is used to simulate the operation of the gate signal conditioning circuit and is monitored.

The utility model provides an asymmetric high-reliability trench gate silicon carbide VDMOS. The asymmetric high-reliability trench gate silicon carbide VDMOS is characterized in that a drift layer is connected to a silicon carbide substrate; the P-type well region is connected to the drift layer; the shunt region is connected to the drift layer and located at the lower left corner of the first groove, and the P-type base region is connected to the shunt region and located at the left side of the first groove; the P-type source region is connected to the P-type well region; the N-type source region is respectively connected with the P-type well region, the P-type base region and the P-type source region; the Schottky metal layer is connected to the drift layer, the P-type well region and the N-type source region; the outer side surface of the insulating dielectric layer is respectively connected with a P-type source region, an N-type source region, a P-type well region, a P-type base region and a shunt region; a groove is formed in the insulating medium layer; the gate metal layer is arranged in the groove; the source metal layer is respectively connected with the P-type source region, the N-type source region and the Schottky metal layer; the drain metal layer is connected to the silicon carbide substrate, so that the characteristics of the device after conduction are ensured at one side, the follow current characteristics of the diode of the device body are ensured at one side, and the reliability of the device is improved.

This application discloses a SiC MOSFET, a SiC MOSFET preparation method, and an integrated circuit. In the SiC MOSFET, a gate electrode is located on two sides of a fin-shaped channel layer. Disposing the gate electrode on the two sides of the fin-shaped channel layer is conducive to reducing a width of the fin-shaped channel layer. This is favorable for global inversion of the fin-shaped channel layer, thereby forming a large carrier path in the fin-shaped channel layer. In this way, most carriers in the SiC MOSFET flow through an electron path formed in the fin-shaped channel layer, so that a quantity of carriers that flow on an edge of a gate oxide layer is reduced, thereby greatly improving channel mobility and also improving reliability of the gate oxide layer.