870 results about "Turn on time" patented technology

A method for reducing the harmonics contents of an input current drawn from a power line into an electrical system without sensing an input voltage, the method comprising providing an active power factor correction controller with a switch module having a main switch and a timing device, wherein the main switch has an on-time correlated with an on-duty cycle duration, and an off-time correlated with an off-duty cycle duration, and maintaining a linear relationship between the off-duty cycle duration and the input current by using the timing device; and an apparatus for active power factor correction with minimum input current distortion, comprising an active power factor correction assembly that includes a main switch and a timing device, wherein the main switch has associated therewith an on-time correlated with an on-duty cycle duration, and an off-time correlated with an off-duty cycle duration, and wherein the timing device generates the mentioned on-time and off-time, and linearization means for maintaining a linear relation between the off-duty cycle duration and the input current.

The main circuit of each stage of the high-reliability shift register circuit is composed of transistors, and the turn-on time for the four transistors are only 1˜2 pulse time within one frame time. Transistors construct an inverter circuit which continuously offers a high-level supply voltage that controls activities of transistors so as to continuously offer a low-level supply voltage to the first node and the output terminal such that avoids the first node and the output terminal being in a floating state. Besides, one of the transistor acts as a charging circuit that extends the lifetime of another transistor. This circuit avoids the affection on the behavior of the shift register circuit that is caused by an a-Si (amorphous silicon) TFT under a sustained stress.

A hysteretic buck converter provides improved regulation control, in particular for buck converter standby operation. A comparison circuit compares the output voltage of the buck converter to a waveform that is generated from an indication of the output current of the converter, so that the turn-on time of the converter is advanced as the output current demand increases. The resulting action anticipates a reduction in output voltage due to the increased current, preventing an excursion of the output voltage below the ripple voltage minimum. The turn-off time of the converter is controlled by an upper threshold that limits the ripple voltage maximum. The output current indication may be a measurement of output current, or may be a dynamic value calculated from the input voltage and the output voltage waveform.

A driving method and apparatus for a liquid crystal display for minimizing motion blur in a moving picture as well as displaying a fresh and dynamic image is disclosed. In the driving method, data inputted from the exterior are converted into brightness components to produce a histogram for each frame. A control value is extracted from various characteristics of the histogram. Turn-on times of a plurality of lamps positioned in such a manner to overlap with a liquid crystal display panel are controlled in correspondence with the control value.

A DC-DC converter including a Pulse Width Modulation (PWM) controller for converting an input voltage into an output voltage is provided. The PWM controller includes an error amplifier, a comparator, a PWM generator and a ramp generator. The error amplifier generates an error signal according to a difference between a reference voltage and the output voltage. The comparator compares the error signal with a ramp signal to generate a trigger signal. The PWM generator generates a PWM signal with a fixed turn-on time, wherein a frequency of the PWM signal is adjusted according to the trigger signal, the input and output voltages. The ramp generator generates the ramp signal according to the PWM signal, the input voltage and the output voltage.

One embodiment of the present invention provides a system that reduces data burst overhead in an Ethernet passive optical network which includes a central node and at least one remote node, wherein downstream data from the central node is broadcast to the remote nodes, and wherein upstream data from a remote node is transmitted to the central node in a unicast manner. During operation, the central node transmits grant messages to a number of remote nodes, wherein a grant message for a specified remote node assigns a start time and a duration of a transmission timeslot in which the specified remote node may transmit an upstream data burst. In response to the grant messages, the central node then receives a number of upstream data bursts, wherein the time gap between two consecutive upstream data bursts is less than the summation of a default laser turn-on time, a default laser turn-off time, an AGC period, and a CDR period.

A power supply circuit for operating high-efficiency lighting devices from a thyristor-controlled dimmer determines the dimming value, i.e., the dimmer duty factor by periodically probing the dimmer output. A minimum conductance is applied across the output of the dimmer during probing intervals that begin at the turn-on time of the dimmer and last until enough information has been gathered to correctly predict a next zero crossing of the AC line voltage that supplies the input of the dimmer. The dimming value is determined from the time interval between the predicted zero-crossing and a next turn-on time of the dimmer. The probing can be performed at intervals of an odd number of half-cycles of the AC line frequency so that a DC offset is not introduced within internal timing circuits of the dimmer. The AC line frequency can also be determined from a time interval between the predicted zero crossings.

A repair path is established between a sub-pixel with a defective drive transistor and another sub-pixel with an operable drive transistor to connect storage capacitors in the two sub-pixels in parallel. Another repair path is established to operate a light emitting device by the operable drive transistor of the second sub-pixel. Terminals of the storage capacitors in the two pixels are connected to a gate of the operable drive transistor. The voltage at the terminals of the storage capacitors are maintained above the threshold voltage of the operable drive transistor is switched on for a longer time due to the combined capacitance of the two storage capacitance. Hence, the sub-pixel with the defective drive transistor and the other sub-pixel of the operable drive transistor remain turned on for a longer time. Hence, despite providing a lower level of current to each of the light emitting devices in the two sub-pixels, the intensity of light produced remains relatively high due to increased turn on time of the operable drive transistor.

A fixing control device includes a power distribution controller that adjusts a power distribution time period when the power is distributed to plural heater elements per control cycle, a turn on time determining member that determines a time when each of the plural heater elements is turned on based on a duty ratio between the power distribution time period and the control cycle, and a soft operation controller that either gradually starts or stops heating each of the plural heater elements during a soft start or stop period, respectively. One of the soft start and stop periods for one of the plural heater elements is decreased not to overlap with another one of the plural heater elements.

An improved valley-mode switching (VMS) scheme and circuitry for implementing the improved VMS switching scheme in a switch-mode power converter are disclosed. For a given switching cycle, a desired switch turn-on time is determined based on a pulse width modulation, pulse frequency modulation, or other suitable power converter control scheme. Also, one or more times corresponding to local minimums (valleys) are predicted for the voltage across a power switch of the switching power converter. The power switch is turned on at a valley immediately subsequent or otherwise subsequent to the desired switch time determined according to the power converter control scheme. Thus, the improved VMS scheme enables low-voltage switch operation to reduce switching loss and EMI noise without restricting the control scheme of the power converter.

The present disclosure discloses a bleeder circuit and a control method thereof, and an LED control circuit. The present disclosure is applied in an LED control circuit of TRIAC dimming, directly or indirectly detects cross-zero point of input voltage; after cross-zero point of the input voltage is delayed by a second time, the bleeder module works to generate bleeder current, and a time between turn-on time of the TRIAC and a time that a driving circuit input current achieves a predetermined value (maintaining current of TRIAC) is a first time. During the first time, the bleeder circuit generates losses; when the first time is greater than a predetermined value, the second time is prolonged; when the first time is smaller than the predetermined value, the second time is reduced, such that the first time is close to or equal to the predetermined value. By using the present disclosure, the second time, which is used as the delay time, is self-adaptively adjusted according to the first time and the predetermined value, and the bleeder power consumption is reduced and system efficiency is enhanced.

An illumination system correlates solar time to a clock and controls lighting or illumination based on time. The illumination system may turn ON light source(s) at a first level at a turn ON time, correlated to be around or at dusk, and turn OFF light source(s) at a turn OFF time, correlated to be around or at dawn. The illumination system may reduce a level of light output, and hence power consumption, at a time after turning ON a light source, and increases the level of light output at a time prior to turning OFF the light source. Turn ON, turn OFF, decrease and increase times may be determined based on recent levels of light or illumination in the environment, for example via average or median levels over a number of previous daily cycles. Filtering may eliminate aberrant events.

To provide an illuminator for plant growth that can illuminate a plant intermittently (pulse illumination) or continuously to cause an effect similar to sunbeam spot phenomenon, thereby accelerating photosynthetic reaction.

Specifically, the illuminator for plant growth includes a light source composed of a semiconductor optical device, a control unit for outputting a turn-on timing signal for the light source, a rhythm signal detecting unit for A/D converting an input rhythm signal, a timing signal modulating unit for modulating the turn-on timing signal with the output signal from the rhythm signal detecting unit, and a pulse drive unit for pulse-modulating a power signal with the modulated turn-on timing signal outputted from the timing signal modulating unit and supplying the pulse-modulated power signal to the light source.

An apparatus for transmitting data for visible light communication sets up the pulse width control step of pulse width modulation (PWM) in a unit time interval, modulates each symbol of VLC source data input into a PWM signal in accordance with the pulse width control step, generates a visible light modulation signal by controlling the turn-on time or turn-off time of a plurality of light emitting diodes (LEDs) in response to the PWM signal, and transmits the visible light modulation signal.

A light emitting device driving circuit, includes: a switch device, a comparator, a driving module, a time counting circuit and a compensation module. The switch device is turned on or off according to a control signal for controlling a driving current flowing through the light emitting device. The comparator generates a comparison result according to a reference voltage and a feedback voltage corresponding to the driving current. The driving module generates the control signal according to the comparison result. The time counting circuit controls the driving module to turn on the switch device after the switch device turns off for a predetermined time. The compensation module detects a turn on time for the switch device and a delay time between the feedback voltage reaching the reference voltage value and the control signal varying correspondingly, and adjusts the reference voltage according to the turn on time and the delay time.

The present invention is a load balancing and distributing switch-on/turn-on control for a circuit breaker, an appliance, a device, or an apparatus wherein each switch-on device on a circuit breaker, appliance, device, or apparatus generates and provides a turn-on time delay up to a maximum turn-on time delay so that the turn-on times and respective loads after a power failure from all circuit breakers, appliances, devices, and/or apparatuses are distributed and/or balanced over a turn-on period. The present invention distributes and balances the load and consumption by various appliances, devices, and apparatuses at the time of initial power up after a power failure. The present invention also distributes the turn-on times of the various appliances, devices, and apparatuses at the initial power up time. A circuit system and method for load balancing and distributing switch-on control of an operating device. A micro-controller is able to couple to the operating device and to a power-in bus for receiving power from a power source. A relay switch system is coupled to the micro-controller for controlling the power from the power-in bus. The relay switch system is able to couple to a power-out bus to control the power to the operating device. The micro-controller generates a power-up delay time through which the micro-controller must wait and control the relay switch system to hold the power to the power-out bus before the relay switch is released to supply the power to the power-out bus for operation of the operating device.

A Wi-Fi module provided in the portable terminal is controlled in such a manner that it is turned on or turned off according to a type setting information item including a setup value defining at least one of: a turn-on time interval of the Wi-Fi module, a turn-off time interval of the Wi-Fi module, and a frequency scanning period of the Wi-Fi module in the turn-on status, and scanning is executed according to the set frequency scanning period in the turn-on status.

An integrated circuit memory device, system and method turns on an output driver in response to a stored value that represents an amount of time from when the output driver is in an operational state to when the output driver begins to output valid read data in various embodiments. An output driver outputs valid read data after a settling amount of time. The sum of the amount of time from when the memory device receives a read command to when the output driver is turned-on and the settling amount of time, is approximately the time from receiving the read command, to at least beginning to provide valid read data at the output of the integrated circuit memory device. A read command is provided to the integrated circuit memory device by a memory controller. In an embodiment, the memory controller also provides or programs the value that represents the amount of time from when the output driver is in an operational state to when the output driver begins to output valid read data.

A 3-dimensional (3D) image display device includes a liquid crystal panel configured to alternately display a left-eye image and a right-eye image in a cycle of unit frame period, a data driving circuit configured to drive data lines of the liquid crystal panel, a gate driving circuit configured to drive gate lines of the liquid crystal panel, a timing controller configured to divide the unit frame period into N sub-frame periods for each of the left-eye image and the right-eye image, where N is an integer equal to or greater than 2, a plurality of light sources configured to generate light to be radiated to the liquid crystal panel, a light source control circuit configured to generate a backlight control signal to control a turn-on time of the plurality of light sources, and a light source driving circuit configured to turn off all the light sources during a first N-1 subframe periods and turn on all the light sources during a last subframe period.