Chip reference voltage trimming circuit

Abstract

The invention discloses a chip reference voltage trimming circuit which is characterized in that when an enable signal is in a high level, a low enable discharge module is turned off, and an adjustable buffer unit generates a preset voltage according to an external reference voltage and a voltage regulating signal; the generated preset voltage generates a reference voltage after passing through a low-pass filtering network consisting of a fast charging path, a slow charging path and a filtering capacitor; the abnormal state detection unit is used for detecting the abnormity of the trimming circuit, if abnormity exists, the output signal of the abnormal state detection unit is high level, the output signal of the quick charging control unit is controlled to be low level, the quick charging access is opened, and the opening time of the quick charging access is controlled through the quick charging control unit; and a following speed trimming signal is input to the fast charging control unit, and the generated reference voltage is trimmed to be the same as the preset voltage. The performance of the reference voltage of the chip is adjusted through the trimming signal, and the performance requirements of equipment in different working states can be met.

Description

Technical Field

[0001] The present invention relates to the technical field of analog circuits and semiconductor integrated circuits, and in particular to a chip reference voltage trimming circuit. Background Art

[0002] With the advancement of information technology and the popularization of 5G networks, a new generation of high-performance electronic devices is required to operate at higher frequencies and have higher signal-to-noise ratios. The noise on the power supply and the intrinsic noise of the device will significantly affect the performance of electronic devices. The reference voltage of the chip, as the reference of the entire circuit or system, not only requires the reference voltage to have good anti-interference ability, but also to meet the needs of the device under different working conditions. Therefore, the performance of the power supply reference voltage needs to be adjusted.

[0003] Figure 1 The invention discloses a reference voltage generating circuit proposed in a bandgap reference circuit and its control method and a power supply circuit with a publication number of CN113721690A. A starting current is injected into a first-stage reference module through a starting circuit module, so that the first-stage reference module escapes from a zero state and generates a first-stage reference voltage. A pre-regulated low voltage difference linear regulator generates a second voltage signal LVDD capable of suppressing power supply noise based on the first-stage reference voltage, and supplies power to a second-stage reference module at the same time. The scheme realizes a reference voltage with low noise and high power supply rejection ratio at the output end of the second-stage reference module by stacking and cascading circuits. However, the circuit has no trimming circuit, and cannot trim the performance of the reference voltage according to a specific working state, thereby failing to adjust the performance of the chip, failing to meet the needs of the equipment, and reducing the yield of the chip. Summary of the invention

[0004] In view of the problems existing in the prior art, the present invention provides a chip reference voltage adjustment circuit, which introduces multiple adjustment signals to adjust the performance of the chip reference voltage to meet the performance requirements of the device under different working conditions.

[0005] To achieve the above technical objectives, the present invention adopts the following technical solutions: A chip reference voltage trimming circuit, comprising: an adjustable buffer unit, an abnormal state detection unit, a fast charge control unit, a fast charge path, a slow charge path, a filter capacitor C1 and a low enable discharge module; When the enable signal EN is at a high level, the low enable discharge module is turned off, and the adjustable buffer unit is turned off according to the external reference voltage V REF and the voltage regulation signal to generate a preset voltage V REF_PRE , the preset voltage V REF_PRE The reference voltage V is generated after passing through the low-pass filter network composed of the fast charging path, the slow charging path and the filter capacitor C1. REF_RC ; The abnormal state detection unit is used for abnormal detection of the adjustment circuit. If there is an abnormality, the output signal SH of the abnormal state detection unit is high level, the output signal ON of the fast charge control unit is controlled to be low level, the fast charge path is opened, the fast charge control unit controls the opening time of the fast charge path, and inputs the follow speed adjustment signal to the fast charge control unit, and the generated reference voltage V REF_RC Adjust to the preset voltage V REF_PRE same.

[0006] Furthermore, when the enable signal EN is at a low level, the low enable discharge module is turned on, and the charge on the filter capacitor C1 flows to the preset voltage V through the low enable discharge module. REF_PRE , and the preset voltage V REF_PRE Discharged to ground by low enable discharge module.

[0007] Furthermore, when the fast charge path is in the off state, the preset voltage V REF_PRE The slow charging path of the trimmed signal through the input filter resistor and the filter capacitor C1 generates a reference voltage V with low noise and high power supply rejection ratio characteristics. REF_RC .

[0008] Furthermore, the adjustable buffer unit includes: an operational amplifier A1, a sixth PMOS tube MP6, a first resistor R1, and an adjustable resistor R2, wherein the in-phase input terminal of the operational amplifier A1 is respectively connected to one end of the first resistor R1 and one end of the adjustable resistor R2, the other end of the first resistor R1 is grounded, and the inverting input terminal of the operational amplifier A1 is connected to an external reference voltage V REF The output end of the operational amplifier A1 is connected to the gate of the sixth PMOS tube MP6, the source of the sixth PMOS tube MP6 is connected to the power supply voltage VIN, the drain of the sixth PMOS tube MP6 and the other end of the adjustable resistor R2 are connected to the low-enable discharge module, the input end of the fast charging path and the input end of the slow charging path as the output end of the adjustable buffer unit; the resistance of the adjustable resistor R2 is controlled by the y-path voltage regulation signal, and the control end of the operational amplifier A1 is connected to the enable signal EN.

[0009] Further, the abnormal state detection unit includes: a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a current source I1, a first capacitor C2, a second capacitor C3, a first Schmidt inverter SMIT1, a first inverter INV1 and an OR gate NOR1, the gate of the fourth NMOS tube MN4 and the input end of the first inverter INV1 are both connected to the enable signal EN, the The source of the fourth NMOS tube MN4 is connected to the input end of the current source I1, and the output end of the current source I1 is grounded; the drain of the fourth NMOS is respectively connected to the gate of the fifth PMOS tube PM5, the drain of the fifth PMOS tube PM5, the gate of the fourth PMOS tube MP4, the gate of the third PMOS tube MP3, the gate of the second PMOS tube MP2, and the gate of the first PMOS tube MP1; the source of the first PMOS tube MP1, the source of the second PMOS tube MP2, the source of the third PMOS tube MP3, the source of the fourth PMOS tube MP4, and the source of the fifth PMOS tube MP5 are all connected. The fourth PMOS tube MP4 and the output of the OR gate NOR1 are connected to the fast charge control unit; the drain of the third PMOS tube MP3 are respectively connected to one end of the second capacitor C3, the input end of the first Schmidt inverter SMIT1, and the drain of the third NMOS tube MN3, the other end of the third capacitor C3 and the source of the third NMOS tube MN3 are grounded, and the gate of the third NMOS tube MN3 is connected to the output end of the first inverter INV1; the output end of the first Schmidt inverter SMIT1 is connected to the first input end of the OR gate NOR1; the third The drains of the two PMOS transistors MP2 are respectively connected to one end of the first capacitor C2, the drain of the second NMOS transistor MN2, and the second input end of the OR gate NOR1; the other end of the first capacitor C2 and the source of the second NMOS transistor MN2 are both grounded; the gate of the second NMOS transistor MN2 is connected to the output end of the operational amplifier A1 in the adjustable buffer unit; the drain of the first PMOS transistor MP1 is respectively connected to the drain of the first NMOS transistor MN1 and the gate of the first NMOS transistor MN1; the source of the first NMOS transistor MN1 is grounded; the third input end of the OR gate NOR1 is connected to the y-path voltage regulation signal.

[0010] Furthermore, the fast charging control unit includes: a fifth NMOS tube MN5, a third capacitor C4, a second Schmidt inverter SMIT2 and a second inverter INV2, the gate of the fifth NMOS tube MN5 is connected to the output end of the OR gate NOR1, the drain of the fifth NMOS tube MN5 is respectively connected to the drain of the fourth PMOS tube MP4, one end of the third capacitor C4, and the input end of the second Schmidt inverter SMIT2, the other end of the third capacitor C4 and the source of the fifth NMOS tube MN5 are both grounded, the output end of the second Schmidt inverter SMIT2 is connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 is connected to the fast charging path.

[0011] Furthermore, the low-enable discharge module includes: a sixth NMOS tube MN6 and a seventh NMOS tube MN7, the drain of the sixth NMOS tube MN6 and the drain of the seventh NMOS tube NM7 are both connected to the output end of the adjustable buffer unit; the source of the sixth NMOS tube MN6 is grounded, and the source of the seventh NMOS tube MN7 is respectively connected to the output end of the fast charging path, the output end of the slow charging path, and one end of the filter capacitor C1; the gate of the sixth NMOS tube MN6 and the gate of the seventh NMOS tube NM7 are both connected to the output end of the first inverter INV1.

[0012] Furthermore, the fast charging path includes: m+1 tenth PMOS tubes, m eleventh PMOS tubes, and m+1 second resistors RA. The gates of the m+1 tenth PMOS tubes are connected to the output end of the second inverter INV2 in the fast charging control unit, and the sources of the m+1 tenth PMOS tubes are connected to the output end of the adjustable buffer unit as the input end of the fast charging path; the drain of the first tenth PMOS tube is connected to one end of the first second resistor RA, and the drains of the last m tenth PMOS tubes are respectively connected to the source of an eleventh PMOS tube, the gates of the m eleventh PMOS tubes are respectively connected to a follow-up speed adjustment signal, and the drains of the m eleventh PMOS tubes are respectively connected to one end of the last m second resistors RA; the other ends of the m+1 second resistors RA are all used as the output end of the fast charging path to generate a reference voltage V REF_RC , and connected to one end of the filter capacitor C1.

[0013] Further, the slow charging path includes: a seventh PMOS tube MP7, an eighth PMOS tube MP8, a ninth PMOS tube MP9, a third resistor R3, an eighth NMOS tube MN8, a ninth NMOS tube MN9, n twelfth PMOS tubes and n tenth NMOS tubes, the source of the seventh PMOS tube MP7, the source of the ninth PMOS tube MP9 and the source of the n twelfth PMOS tubes are all connected to the output end of the adjustable buffer unit as the input end of the slow charging path; the drain of the seventh PMOS tube MP7 is connected to the source of the eighth PMOS tube MP8, the gate of the seventh PMOS tube MP7, the gate of the eighth PMOS tube MP8, the gate of the ninth PMOS tube MP9 and the drain of the ninth PMOS tube MP9 are all connected to the drain of the ninth NMOS tube MN9, the drain of the eighth PMOS tube MP8 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is used as the output end of the slow charging path to generate a reference voltage V REF_RC , and connected to one end of the filter capacitor C1; the gate of the ninth NMOS tube MN9, the gate of the eighth NMOS tube MN8 and the gates of the n tenth NMOS tubes are all connected to the gate of the first NMOS tube MN1 in the abnormal state detection unit, the source of the ninth NMOS tube MN9 and the source of the n tenth NMOS tubes are all connected to the drain of the eighth NMOS tube MN8, and the source of the eighth NMOS tube MN8 is grounded; the drains of the n tenth NMOS tubes are respectively connected to the drain of a twelfth PMOS tube, and the gates of the n twelfth PMOS tubes are respectively connected to a filter resistance adjustment signal.

[0014] Furthermore, the other end of the filter capacitor C1 is grounded.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The chip reference voltage trimming circuit of the present invention generates a preset voltage according to an adjustable buffer unit of an input voltage regulation signal, and by introducing a follow-up speed trimming signal and a filter resistor trimming signal, the noise, power supply rejection ratio, follow-up speed and other performances of the preset voltage are carefully trimmed to obtain a reference voltage, which can not only meet the performance requirements of the chip under different working conditions, but also improve the yield of the chip; The chip reference voltage trimming circuit of the present invention is also provided with an abnormal state detection unit to realize abnormal detection of the trimming circuit and open the fast charging path. By controlling the opening time of the fast charging path, the reference voltage is quickly trimmed to the same as the preset voltage, so that the chip quickly reaches a stable state and ensures the normal operation of the chip. The chip reference voltage trimming circuit of the present invention is also provided with a low-enable discharge module, which provides a discharge path for the reference voltage when the trimming circuit is low-enabled, so that there is no reference residual voltage that affects the performance of the subsequent circuit, thereby ensuring the safety and stability of the subsequent circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of a reference voltage generating circuit in the prior art; Figure 2 A schematic diagram of a chip reference voltage trimming circuit of the present invention; Figure 3 It is a circuit diagram of the abnormal state detection unit and the fast charging control unit in the present invention; Figure 4 A circuit diagram of an adjustable buffer unit and a low-enable discharge module in the present invention; Figure 5 It is a circuit diagram of the low-pass filter network in the present invention. DETAILED DESCRIPTION

[0017] The technical solution of the present invention is further explained below in conjunction with the accompanying drawings.

[0018] like Figure 2 Schematic diagram of a chip reference voltage trimming circuit of the present invention, the trimming circuit includes: an adjustable buffer unit 101, an abnormal state detection unit 102, a fast charge control unit 103, a fast charge path 104, a slow charge path 105, a filter capacitor C1106 and a low enable discharge module 107; When the enable signal EN is at a high level, the low enable discharge module 107 is turned off, and the adjustable buffer unit 101 is turned off according to the external reference voltage V REF and the voltage regulation signal to generate a preset voltage V REF_PRE , the preset voltage V REF_PRE The reference voltage V is generated after passing through the low-pass filter network composed of the fast charge path 104, the slow charge path 105 and the filter capacitor C1 106. REF_RC Specifically, the fast charge path 104 is a low impedance path, which is controlled by the output signal ON of the fast charge control unit 103 and is used to quickly charge the filter capacitor C1 106, so that the reference voltage V REF_RC Rapid establishment; when the fast charging path 104 is closed, the low-pass filter network is composed of a high-impedance slow charging path 105 and filter capacitors C1 106, and the preset voltage V REF_PRE After the input filter resistor adjusts the signal through the slow charging path 105 and the filter capacitor C1 106, the preset voltage V output by the adjustable buffer unit 101 is REF_PRE The reference voltage V has low noise and high power supply rejection ratio. REF_RC , which can effectively suppress the noise on the power supply and the intrinsic noise of the device, and improve the anti-interference ability of the chip.

[0019] The abnormal state detection unit 102 is used to detect abnormalities in the adjustment circuit. If an abnormality exists, the output signal SH of the abnormal state detection unit 102 is high level, and the output signal ON of the fast charge control unit 103 is controlled to be low level, and the fast charge path 104 is opened. The fast charge control unit 103 controls the opening time of the fast charge path 104, and inputs the follow speed adjustment signal to the fast charge control unit 103 to ensure that the reference voltage V REF_RC Can quickly follow the preset voltage V REF_PRE changes and fully stabilizes to the preset voltage V REF_PRE .

[0020] When the enable signal EN is at a low level, the low enable discharge module 107 is turned on, and the charge on the filter capacitor C1 106 flows to the preset voltage V through the low enable discharge module 107. REF_PRE , and the preset voltage V REF_PRE The low-enable discharge module 107 discharges to the ground, so that there is no reference residual voltage that affects the performance of the subsequent circuit, thereby avoiding unknown risks to the chip.

[0021] The present invention introduces a variety of adjustment signals based on the chip reference voltage adjustment circuit to adjust the performance of the reference voltage, which can not only meet the performance requirements of the chip under different working conditions, but also improve the yield of the chip.

[0022] like Figure 4 The adjustable buffer unit 101 includes: an operational amplifier A1, a sixth PMOS tube MP6, a first resistor R1, and an adjustable resistor R2. The in-phase input terminal of the operational amplifier A1 is connected to one end of the first resistor R1 and one end of the adjustable resistor R2 respectively, the other end of the first resistor R1 is grounded, and the inverting input terminal of the operational amplifier A1 is connected to the external reference voltage V REF The output end of the operational amplifier A1 is connected to the gate of the sixth PMOS tube MP6, the source of the sixth PMOS tube MP6 is connected to the power supply voltage VIN, the drain of the sixth PMOS tube MP6 and the other end of the adjustable resistor R2 are connected as the output end of the adjustable buffer unit 101 to the low-enable discharge module 107, the input end of the fast charging path 104 and the input end of the slow charging path 105; the resistance of the adjustable resistor R2 is controlled by the y-way voltage regulation signal, and the control end of the operational amplifier A1 is connected to the enable signal EN. By setting the voltage regulation signal, the buffer unit 101 can output a high-precision preset voltage V REF_PRE , V REF_PRE =[1+(R2) / (R1)]×V REF .

[0023] like Figure 3The abnormal state detection unit 102 includes: a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a current source I1, a first capacitor C2, a second capacitor C3, a first Schmidt inverter SMIT1, a first inverter INV1 and an OR gate NOR1. The gate of the fourth NMOS tube MN4 and the input end of the first inverter INV1 are both connected to the enable signal EN. The fourth NMOS tube MN4 is connected to the enable signal EN. The source of the S transistor MN4 is connected to the input end of the current source I1, and the output end of the current source I1 is grounded; the drain of the fourth NMOS is respectively connected to the gate of the fifth PMOS transistor PM5, the drain of the fifth PMOS transistor PM5, the gate of the fourth PMOS transistor MP4, the gate of the third PMOS transistor MP3, the gate of the second PMOS transistor MP2, and the gate of the first PMOS transistor MP1; the source of the first PMOS transistor MP1, the source of the second PMOS transistor MP2, the source of the third PMOS transistor MP3, the source of the fourth PMOS transistor MP4, and the source of the fifth PMOS transistor MP5 are all connected to the power supply voltage VI N connection; the drain of the fourth PMOS tube MP4 and the output end of the OR gate NOR1 are connected to the fast charging control unit 103; the drain of the third PMOS tube MP3 is respectively connected to one end of the second capacitor C3, the input end of the first Schmitt inverter SMIT1, and the drain of the third NMOS tube MN3, the other end of the third capacitor C3 and the source of the third NMOS tube MN3 are grounded, and the gate of the third NMOS tube MN3 is connected to the output signal ENL of the output end of the first inverter INV1; the output end of the first Schmitt inverter SMIT1 is connected to the first input end of the OR gate NOR1; the second PMOS tube The drain of MP2 is respectively connected to one end of the first capacitor C2, the drain of the second NMOS transistor MN2, and the second input end of the OR gate NOR1; the other end of the first capacitor C2 and the source of the second NMOS transistor MN2 are both grounded; the output signal PGATE of the gate of the second NMOS transistor MN2 is connected to the output end of the operational amplifier A1 in the adjustable buffer unit 101; the drain of the first PMOS transistor MP1 is respectively connected to the drain of the first NMOS transistor MN1 and the gate of the first NMOS transistor MN1, and the source of the first NMOS transistor MN1 is grounded; the third input end of the OR gate NOR1 is connected to the y-path voltage regulation signal.

[0024] The abnormal state detection unit 102 can perform three abnormal state detections: The first is that the enable signal EN flips from low to high: when the enable signal EN is low, the fourth NMOS tube MN4 is turned off, the current mirror composed of the first PMOS tube MP1 to the fifth PMOS tube MP5 is turned off, and no current charges the second capacitor C3; at the same time, the third NMOS tube MN3 is turned on, and the second capacitor C3 is discharged through the third NMOS tube MN3, so that the input terminal signal of the first Schmidt inverter SMIT1 is 0; when the enable signal EN flips from low to high, the third NMOS tube MN3 is turned off, the fourth NMOS tube MN4 is turned on, and the current mirror charges the second capacitor C3, but a certain delay is required for the first Schmidt inverter SMIT1 to reach the flip threshold, so during this period of time, the input terminal signal of the first Schmidt inverter SMIT1 is still 0, so that the output signal SH of the OR gate NOR is high level, that is, the abnormal state is detected by the abnormal state detection unit 102.

[0025] The second is that the power supply voltage VIN is lower than the preset voltage V output by the adjustable buffer unit 101. REF_PRE : In this state, the output voltage of the operational amplifier A1 is 0, the second NMOS tube MN2 is turned off, and the current mirror charges the first capacitor C2, and quickly pulls the end connected to the first capacitor C2, the drain of the second NMOS tube MN2, and the drain of the second PMOS tube MP2 to a high level, so that the output signal SH of the OR gate NOR is a high level, that is, the abnormal state is detected by the abnormal state detection unit 102.

[0026] The third is any change in the voltage regulation signal: when any change occurs in the y-channel voltage regulation signal, a high-level pulse signal is output, so that the output signal SH of the OR gate NOR is high, that is, the abnormal state is detected by the abnormal state detection unit 102.

[0027] like Figure 3The fast charging control unit 103 includes: a fifth NMOS tube MN5, a third capacitor C4, a second Schmidt inverter SMIT2 and a second inverter INV2. The gate of the fifth NMOS tube MN5 is connected to the output end of the OR gate NOR1, the drain of the fifth NMOS tube MN5 is respectively connected to the drain of the fourth PMOS tube MP4, one end of the third capacitor C4, and the input end of the second Schmidt inverter SMIT2. The other end of the third capacitor C4 and the source of the fifth NMOS tube MN5 are both grounded. The output end of the second Schmidt inverter SMIT2 is connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 is connected to the fast charging path 104. When an abnormal state is detected, the output signal SH of the abnormal state detection unit 102 is high, the fifth NMOS tube MN5 is turned on, and the charge on the third capacitor C4 is quickly discharged to the ground through the fifth NMOS tube MN5, and then the output signal ON is low after passing through the second Schmitt inverter SMIT2 and the second inverter INV2, thereby opening the fast charging path 104; when the abnormal state ends, the output signal SH of the abnormal state detection unit 102 is low, the fifth NMOS tube MN5 is turned off, and the third capacitor C4 is charged through the fourth PMOS tube MP4. When the level on the third capacitor C4 reaches the flip threshold of the second Schmitt inverter SMIT2, the second Schmitt inverter SMIT2 outputs a low level, and the output terminal signal ON of the second inverter INV2 is high, so that the fast charging path 104 is turned off. The present invention controls the size of the charging current through the third capacitor C4 and the fourth PMOS tube MP4, and can control the opening time of the fast charging path 104, thereby ensuring the reference voltage V REF_RC Fully stabilized to the preset voltage V REF_PRE .

[0028] like Figure 4 , the low enable discharge module 107 includes: a sixth NMOS tube MN6 and a seventh NMOS tube MN7, the drain of the sixth NMOS tube MN6 and the drain of the seventh NMOS tube NM7 are both connected to the output end of the adjustable buffer unit 101; the source of the sixth NMOS tube MN6 is grounded, and the source of the seventh NMOS tube MN7 is respectively connected to the output end of the fast charge path 104, the output end of the slow charge path 105, and one end of the filter capacitor C1 106; the gate of the sixth NMOS tube MN6 and the gate of the seventh NMOS tube NM7 are both connected to the output signal ENL of the output end of the first inverter INV1. When the enable signal EN is at a low level, the signal ON output by the fast charge control unit 103 is also at a low level, controlling the fast charge path 104 to be opened, although at this time the preset voltage V REF_PRE and reference voltage V REF_RCThe first and second NMOS transistors MN6 and MN7 are connected through a fast charging path 104. However, since the capacitance of the filter capacitor C1 106 is very large, after the enable signal EN changes from high to low, the filter capacitor C1 106 needs a long time to completely discharge the charge through the low resistance path, and the residual voltage on the filter capacitor C1 106 will deteriorate the performance of the subsequent circuit. The present invention adds a low enable discharge module 107. When the enable signal EN is at a low level, the signal output after the first inverter INV1 is at a high level, the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 are turned on, and the preset voltage V REF_PRE The sixth NMOS tube MN6 discharges to the ground; along with the preset voltage V REF_PRE The charge on the filter capacitor C1106 will flow to the preset voltage V through the seventh NMOS transistor MN7. REF_PRE , and finally discharged to the ground. Since the sixth NMOS tube MN6 and the seventh NMOS tube MN7 are both switch tubes, the impedance is close to zero, so the charge on the filter capacitor C1 106 will be quickly discharged. When the enable signal EN becomes a high level, the sixth NMOS tube MN6 and the seventh NMOS tube MN7 are turned off, which will not affect the normal operation of the trimming circuit.

[0029] like Figure 5 The fast charge path 104 includes: m+1 tenth PMOS tubes AP, m eleventh PMOS tubes BP, and m+1 second resistors RA. The gates of the m+1 tenth PMOS tubes AP are connected to the output end of the second inverter INV2 in the fast charge control unit 103, and the sources of the m+1 tenth PMOS tubes AP are connected to the output end of the adjustable buffer unit 101 as the input end of the fast charge path 104; the drain of the first tenth PMOS tube AP is connected to one end of the first second resistor RA, and the drains of the last m tenth PMOS tubes AP are respectively connected to the source of an eleventh PMOS tube BP, the gates of the m eleventh PMOS tubes BP are respectively connected to a follow-up speed adjustment signal, and the drains of the m eleventh PMOS tubes BP are respectively connected to one end of the last m second resistors RA; the other end of the m+1 second resistors RA are all used as the output end of the fast charge path 104 to generate a reference voltage V REF_RC , and connected to one end of the filter capacitor C1 106, and the other end of the filter capacitor C1 106 is grounded. When the abnormal state detection unit 102 detects an abnormal state, the output signal SH of the abnormal state detection unit 102 is high, the fifth NMOS tube MN5 is turned on, and then the output signal ON of the fast charge control unit is set low, so that the preset voltage V REF_PRE and reference voltage V REF_RC The low resistance fast charge path 104 between is opened, and the reference voltage V REF_RC Can quickly follow the preset voltage V REF_PRESpecifically, the equivalent impedance of the fast charge path 104 is determined by the m+1 second resistors RA, and the m eleventh PMOS tubes BP are controlled by the m-path following speed adjustment signal. By setting the following speed adjustment signal, the reference voltage V REF_RC With the preset voltage V REF_PRE The more PMOS tubes that are turned on in the eleventh PMOS tube BP are controlled by the following speed adjustment signal, the more second resistors RA are connected in parallel to the circuit, and the smaller the equivalent impedance of the fast charging path 104 is, so that the reference voltage V REF_RC With the preset voltage V REF_PRE The faster the change speed. For different application scenarios, the reference voltage V can be adjusted by adjusting the speed adjustment signal. REF_RC After all abnormal states are over, the output signal SH of the abnormal state detection unit 102 is set to 0, the fifth NMOS tube MN5 is turned off, and the fourth PMOS tube MP4 charges the fourth capacitor C4. By setting a reasonable delay, it is ensured that the output signal ON of the fast charging control unit is high level, that is, when the fast charging path 104 is turned off, the reference voltage V REF_RC has been fully stabilized to the preset voltage V REF_PRE .

[0030] like Figure 5 The slow charging path 105 includes: a seventh PMOS tube MP7, an eighth PMOS tube MP8, a ninth PMOS tube MP9, a third resistor R3, an eighth NMOS tube MN8, a ninth NMOS tube MN9, n twelfth PMOS tubes CP and n tenth NMOS tubes CN. The source of the seventh PMOS tube MP7, the source of the ninth PMOS tube MP9 and the source of the n twelfth PMOS tubes CP are all connected to the output end of the adjustable buffer unit 101 as the input end of the slow charging path 105; the drain of the seventh PMOS tube MP7 is connected to the source of the eighth PMOS tube MP8, the gate of the seventh PMOS tube MP7, the gate of the eighth PMOS tube MP8, the gate of the ninth PMOS tube MP9 and the drain of the ninth PMOS tube MP9 are all connected to the drain of the ninth NMOS tube MN9, the drain of the eighth PMOS tube MP8 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is used as the output end of the slow charging path 105 to generate a reference voltage V REF_RC, and connected to one end of the filter capacitor C1 106; the gate of the ninth NMOS tube MN9, the gate of the eighth NMOS tube MN8 and the gates of the n tenth NMOS tubes CN are all connected to the output signal VBN of the gate of the first NMOS tube MN1 in the abnormal state detection unit 102, the source of the ninth NMOS tube MN9 and the source of the n tenth NMOS tubes CN are all connected to the drain of the eighth NMOS tube MN8, and the source of the eighth NMOS tube MN8 is grounded; the drains of the n tenth NMOS tubes CN are respectively connected to the drain of a twelfth PMOS tube CP, and the gates of the n twelfth PMOS tubes CP are respectively connected to a filter resistance adjustment signal. When the fast-pass path 104 is in the off state, the low-pass filter network is only composed of a high-resistance slow-charge path 105 and a large filter capacitor C1 106 in series, and the preset voltage V REF_PRE After passing through the low-pass filter network, a reference voltage V with low noise and high power supply rejection ratio can be obtained. REF_RC Specifically, the current of the eighth NMOS tube MN8 is obtained by continuously copying the external current source I1, and its value is I. The n twelfth PMOS tubes CP are controlled by the n-way filter resistor adjustment signal. By setting the filter resistor adjustment signal, the equivalent resistance value of the slow charging path 105 can be changed. Then, the total width-to-length ratio of the n tenth NMOS tubes CN connected to the circuit is (W / L) CN , the current flowing through the ninth PMOS tube MP9 working in the saturation region is: ,

[0031] in, K represents the process constant, It represents the gate-source voltage difference of the ninth PMOS tube MP9. Indicates the threshold voltage of the PMOS tube; The seventh PMOS tube MP7 and the eighth PMOS tube MP8 work in the linear region, and V GS,MP7 = V GS,MP8 = V GS,MP9 , the impedances of the seventh PMOS tube MP7 and the eighth PMOS tube MP8 are respectively: ,

[0032] Therefore, the equivalent impedance of the slow charging path is R eff =R MP7 + R MP8 +R3, the more PMOS tubes are turned on in the twelfth PMOS tube CP, the more the tenth NMOS tubes CN connected to the corresponding circuits are connected, (W / L) CN The larger the size, that is, the smaller the current flowing through the ninth PMOS transistor MP9 is, the larger the equivalent resistance value of the slow charging path 105 is, and the better the filtering performance is.

[0033] The reference voltage-based trimming circuit of the present invention introduces a variety of trimming signals to finely trim the performance of the reference voltage, which can not only meet the performance requirements of the chip under different working conditions, but also improve the yield of the chip. The resistance value of the adjustable resistor R2 is controlled by the y-path voltage regulation signal. By setting the voltage regulation signal, the adjustable buffer unit 101 can output a high-precision preset voltage V REF_PRE The m eleventh PMOS tubes BP are controlled by the m-way follow speed adjustment signal. By setting the follow speed adjustment signal, the reference voltage V REF_RC With the preset voltage V REF_PRE The more PMOS tubes that are turned on in the eleventh PMOS tube BP, the smaller the equivalent impedance of the fast charging path 104 is, and the reference voltage V REF_RC With the preset voltage V REF_PRE The faster the change speed; the n twelfth PMOS tubes CP are controlled by n filter resistance adjustment signals. By setting the filter resistance adjustment signal, the equivalent resistance value of the slow charging path 105 can be changed. The more PMOS tubes that are turned on in the twelfth PMOS tube CP, the smaller the current flowing through the ninth PMOS tube MP9, the larger the equivalent resistance value of the slow charging path 105, and the better the filtering performance.

[0034] The above are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims

1. A chip reference voltage trimming circuit, characterized in that: include: An adjustable buffer unit (101), an abnormal state detection unit (102), a fast charging control unit (103), a fast charging path (104), a slow charging path (105), a filter capacitor C1 (106) and a low-enable discharge module (107); When the enable signal EN is at a high level, the low enable discharge module (107) is turned off, and the adjustable buffer unit (101) is adjusted according to the external reference voltage V REF and the voltage regulation signal to generate a preset voltage V REF_PRE , the preset voltage V REF_PRE A reference voltage V is generated after passing through a low-pass filter network composed of a fast charging path (104), a slow charging path (105) and a filter capacitor C1 (106). REF_RC ; The abnormal state detection unit (102) is used for detecting abnormalities of the adjustment circuit. If an abnormality exists, the output signal SH of the abnormal state detection unit (102) is high level, the output signal ON of the fast charge control unit (103) is controlled to be low level, the fast charge path (104) is opened, the opening time of the fast charge path (104) is controlled by the fast charge control unit (103), and a follow speed adjustment signal is input to the fast charge control unit (103), so that the generated reference voltage V REF_RC Adjust to the preset voltage V REF_PRE same.

2. A chip reference voltage trimming circuit according to claim 1, characterized in that: When the enable signal EN is at a low level, the low enable discharge module (107) is turned on, and the charge on the filter capacitor C1 (106) flows to the preset voltage V through the low enable discharge module (107). REF_PRE , and the preset voltage V REF_PRE Discharged to ground by the low enable discharge module (107).

3. The chip reference voltage trimming circuit according to claim 1, characterized in that: When the fast charging path (104) is in the off state, the preset voltage V REF_PRE The slow charging path (105) of the input filter resistor trimming signal and the filter capacitor C1 (106) generate a reference voltage V with low noise and high power supply rejection ratio characteristics. REF_RC .

4. The chip reference voltage trimming circuit according to claim 3, characterized in that: The adjustable buffer unit (101) comprises: an operational amplifier A1, a sixth PMOS transistor MP6, a first resistor R1, and an adjustable resistor R2, wherein the in-phase input terminal of the operational amplifier A1 is respectively connected to one end of the first resistor R1 and one end of the adjustable resistor R2, the other end of the first resistor R1 is grounded, and the inverting input terminal of the operational amplifier A1 is connected to an external reference voltage V REF The output end of the operational amplifier A1 is connected to the gate of the sixth PMOS tube MP6, the source of the sixth PMOS tube MP6 is connected to the power supply voltage VIN, the drain of the sixth PMOS tube MP6 and the other end of the adjustable resistor R2 are connected as the output end of the adjustable buffer unit (101) to the low-enable discharge module (107), the input end of the fast charging path (104) and the input end of the slow charging path (105); the resistance value of the adjustable resistor R2 is controlled by the y-path voltage regulation signal, and the control end of the operational amplifier A1 is connected to the enable signal EN.

5. The chip reference voltage trimming circuit according to claim 4, characterized in that: The abnormal state detection unit (102) comprises: a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a current source I1, a first capacitor C2, a second capacitor C3, a first Schmidt inverter SMIT1, a first inverter INV1 and an OR gate NOR1, the gate of the fourth NMOS tube MN4 and the input end of the first inverter INV1 are both connected to an enable signal EN, and the fourth The source of the NMOS tube MN4 is connected to the input end of the current source I1, and the output end of the current source I1 is grounded; the drain of the fourth NMOS is respectively connected to the gate of the fifth PMOS tube PM5, the drain of the fifth PMOS tube PM5, the gate of the fourth PMOS tube MP4, the gate of the third PMOS tube MP3, the gate of the second PMOS tube MP2, and the gate of the first PMOS tube MP1; the source of the first PMOS tube MP1, the source of the second PMOS tube MP2, the source of the third PMOS tube MP3, the source of the fourth PMOS tube MP4, and the source of the fifth PMOS tube MP5 are all connected to the power supply voltage VIN is connected; the drain of the fourth PMOS tube MP4 and the output end of the OR gate NOR1 are both connected to the fast charging control unit (103); the drain of the third PMOS tube MP3 is respectively connected to one end of the second capacitor C3, the input end of the first Schmidt inverter SMIT1, and the drain of the third NMOS tube MN3, the other end of the third capacitor C3 and the source of the third NMOS tube MN3 are both grounded, and the gate of the third NMOS tube MN3 is connected to the output end of the first inverter INV1; the output end of the first Schmidt inverter SMIT1 is connected to the first input end of the OR gate NOR1; the second PMOS tube MP3 is respectively connected to one end of the second capacitor C3, the input end of the first Schmidt inverter SMIT1, and the drain of the third NMOS tube MN3, the other end of the third capacitor C3 and the source of the third NMOS tube MN3 are both grounded, and the gate of the third NMOS tube MN3 is connected to the output end of the first inverter INV1; the output end of the first Schmidt inverter SMIT1 is connected to the first input end of the OR gate NOR1; The drain of the OS transistor MP2 is respectively connected to one end of the first capacitor C2, the drain of the second NMOS transistor MN2, and the second input end of the OR gate NOR1; the other end of the first capacitor C2 and the source of the second NMOS transistor MN2 are both grounded; the gate of the second NMOS transistor MN2 is connected to the output end of the operational amplifier A1 in the adjustable buffer unit (101); the drain of the first PMOS transistor MP1 is respectively connected to the drain of the first NMOS transistor MN1 and the gate of the first NMOS transistor MN1; the source of the first NMOS transistor MN1 is grounded; and the third input end of the OR gate NOR1 is connected to the y-channel voltage regulation signal.

6. The chip reference voltage trimming circuit according to claim 5, characterized in that: The fast charge control unit (103) comprises: a fifth NMOS tube MN5, a third capacitor C4, a second Schmidt inverter SMIT2 and a second inverter INV2; the gate of the fifth NMOS tube MN5 is connected to the output end of the OR gate NOR1; the drain of the fifth NMOS tube MN5 is respectively connected to the drain of the fourth PMOS tube MP4, one end of the third capacitor C4 and the input end of the second Schmidt inverter SMIT2; the other end of the third capacitor C4 and the source of the fifth NMOS tube MN5 are both grounded; the output end of the second Schmidt inverter SMIT2 is connected to the input end of the second inverter INV2; and the output end of the second inverter INV2 is connected to the fast charge path (104).

7. The chip reference voltage trimming circuit according to claim 6, characterized in that: The low-enable discharge module (107) comprises: a sixth NMOS tube MN6 and a seventh NMOS tube MN7, wherein the drain of the sixth NMOS tube MN6 and the drain of the seventh NMOS tube NM7 are both connected to the output end of the adjustable buffer unit (101); the source of the sixth NMOS tube MN6 is grounded, and the source of the seventh NMOS tube MN7 is respectively connected to the output end of the fast charging path (104), the output end of the slow charging path (105), and one end of the filter capacitor C1 (106); and the gate of the sixth NMOS tube MN6 and the gate of the seventh NMOS tube NM7 are both connected to the output end of the first inverter INV1.

8. The chip reference voltage trimming circuit according to claim 7, characterized in that: The fast charging path (104) comprises: m+1 tenth PMOS tubes, m eleventh PMOS tubes, and m+1 second resistors RA; the gates of the m+1 tenth PMOS tubes are connected to the output end of the second inverter INV2 in the fast charging control unit (103); the sources of the m+1 tenth PMOS tubes are connected to the output end of the adjustable buffer unit (101) as the input end of the fast charging path (104); the drain of the first tenth PMOS tube is connected to one end of the first second resistor RA; the drains of the next m tenth PMOS tubes are respectively connected to the source of an eleventh PMOS tube; the gates of the m eleventh PMOS tubes are respectively connected to a follow-up speed adjustment signal; the drains of the m eleventh PMOS tubes are respectively connected to one end of the next m second resistors RA; the other ends of the m+1 second resistors RA are used as the output end of the fast charging path (104) to generate a reference voltage V REF_RC , and connected to one end of the filter capacitor C1 (106).

9. The chip reference voltage trimming circuit according to claim 8, characterized in that: The slow charging path (105) comprises: a seventh PMOS tube MP7, an eighth PMOS tube MP8, a ninth PMOS tube MP9, a third resistor R3, an eighth NMOS tube MN8, a ninth NMOS tube MN9, n twelfth PMOS tubes and n tenth NMOS tubes; the source of the seventh PMOS tube MP7, the source of the ninth PMOS tube MP9 and the source of the n twelfth PMOS tubes are all connected to the output end of the adjustable buffer unit (101) as the input end of the slow charging path (105); the drain of the seventh PMOS tube MP7 is connected to the source of the eighth PMOS tube MP8; the gate of the seventh PMOS tube MP7, the gate of the eighth PMOS tube MP8, the gate of the ninth PMOS tube MP9 and the drain of the ninth PMOS tube MP9 are all connected to the drain of the ninth NMOS tube MN9; the drain of the eighth PMOS tube MP8 is connected to one end of the third resistor R3; the other end of the third resistor R3 is used as the output end of the slow charging path (105) to generate a reference voltage V REF_RC , and connected to one end of the filter capacitor C1 (106); the gate of the ninth NMOS tube MN9, the gate of the eighth NMOS tube MN8 and the gates of the n tenth NMOS tubes are all connected to the gate of the first NMOS tube MN1 in the abnormal state detection unit (102); the source of the ninth NMOS tube MN9 and the source of the n tenth NMOS tubes are all connected to the drain of the eighth NMOS tube MN8, and the source of the eighth NMOS tube MN8 is grounded; the drains of the n tenth NMOS tubes are respectively connected to the drain of a twelfth PMOS tube, and the gates of the n twelfth PMOS tubes are respectively connected to a filter resistance adjustment signal.

10. The chip reference voltage trimming circuit according to claim 9, characterized in that: The other end of the filter capacitor C1 (106) is grounded.

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