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Executing multiple programs simultaneously on a processor core

A processor and execution context technology, applied in machine execution devices, concurrent instruction execution, program control design, etc., can solve problems that do not show continuous improvement in area or performance

Active Publication Date: 2019-09-17
MICROSOFT TECH LICENSING LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Out-of-order superscalar implementations show no consistent improvements in area or performance

Method used

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  • Executing multiple programs simultaneously on a processor core
  • Executing multiple programs simultaneously on a processor core
  • Executing multiple programs simultaneously on a processor core

Examples

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Embodiment Construction

[0019] I. General considerations

[0020] The present invention is illustrated in the context of representative embodiments, which are not intended to be limiting in any way.

[0021] As used in this application, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Additionally, the term "includes" means "comprises". Furthermore, the term "coupled" includes mechanical, electrical, magnetic, optical and other physical means of coupling or linking items together and does not exclude the presence of intervening elements between the coupled items. Also, as used herein, the term "and / or" means any one or combination of items in a phrase.

[0022] The systems, methods and devices described herein should not be construed as limiting in any way. Rather, the present disclosure relates to all novel and non-obvious features and aspects of the various disclosed embodiments both individually and in various combinations and subco...

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PUM

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Abstract

Systems and methods are disclosed for allocating resources to contexts in block-based processor architectures. In one example of the disclosed technology, a processor is configured to spatially allocate resources between multiple contexts being executed by the processor, including caches, functional units, and register files. In a second example of the disclosed technology, a processor is configured to temporally allocate resources between multiple contexts, for example, on a clock cycle basis, including caches, register files, and branch predictors. Each context is guaranteed access to its allocated resources to avoid starvation from contexts competing for resources of the processor. A results buffer can be used for folding larger instruction blocks into portions that can be mapped to smaller-sized instruction windows. The results buffer stores operand results that can be passed to subsequent portions of an instruction block.

Description

Background technique [0001] Due to the continuous transistor scaling predicted by Moore's Law, microprocessors benefit from continuous improvements in transistor count, integrated circuit cost, manufacturing capital, clock frequency, and energy efficiency, with little change in the associated processor instruction set architecture (ISA). However, the benefits of lithography scaling that has powered the semiconductor industry for the past 40 years are slowing or even reversing. For many years, the Reduced Instruction Set Computing (RISC) architecture has been the dominant paradigm for processor design. Out-of-order superscalar implementations show no consistent improvements in area or performance. Therefore, there is ample opportunity to improve processor ISAs to extend performance improvements. Contents of the invention [0002] Methods, apparatus, and computer-readable storage devices are disclosed for processors, including those having a block-based processor instruction...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/30G06F9/38
CPCG06F9/30189G06F9/3814G06F9/3851G06F9/3891Y02D10/00G06F9/3858G06F9/30076G06F9/3885
Inventor G·古普塔D·C·伯格
Owner MICROSOFT TECH LICENSING LLC
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