11 results about "Memory process" patented technology

The invention discloses a novel memristor Baplov associative memory circuit, and belongs to the field of memristor neural networks. Comprising a control module composed of NMOS tubes T1 and T2, diodes D1 and D2 and a resistor R11, a neuron module composed of an NMOS tube T3, a voltage source VDD and a resistor R12, an absolute value circuit composed of operational amplifiers A2 and A3, diodes D3 and D4 and resistors R6, R7, R8, R9 and R10, a voltage following operational amplifier A1 and a learning forgetting module. Aiming at the technical bottlenecks that a current Baplov associative memory circuit depends on a multi-memristor array, is complex in structure and is difficult to realize a multi-type forgetting function, a very simple hardware architecture design is innovatively provided, only one memristor is used as a core memory unit, and a circuit system is constructed by matching a small number of basic electronic devices such as resistors, capacitors and transistors; therefore, three key forgetting modes in the Baplov associative memory process can be efficiently realized.

Enables immediate changes to settings. [Solution] The AF area settings and detection target type settings stored in the memory process are recalled by a specific user operation, and subject detection processing and focus detection processing are executed according to the recalled settings.

The invention provides a method and a system for developing an on-chip memory. The method comprises the following steps: acquiring a memory peripheral circuit demand table and a memory process information table; processing the memory process information table through a first script module and an external script to generate memory data; based on a memory peripheral circuit instance capable of being used as a template, a second script module performs parameter modification and script replacement on the memory peripheral circuits to generate a plurality of memory peripheral circuits and a memory peripheral circuit list; integrating the peripheral circuit of the memory with the whole chip source code; chip circuit simulation is realized by using an EDA tool and memory data; summarizing the memory data through a text extraction script to obtain a memory information collection table; the data of the memory and an RTL circuit in a peripheral circuit of the memory are synthesized and realized; the peripheral circuit of the memory shields process differentiation information; the statistical information can improve the working efficiency of memory development.

This invention discloses a data processing system, method, device, medium, and program product in the field of computer technology. In this invention, the cache coherence root port of the computing device is connected to the cache coherence sub-port of the memory processing device via a cache coherence protocol. This enables the computing device to: synchronize the first result output from the query matrix and key-value matrix calculation stages of the model processing task to the memory processing device via the cache coherence protocol; simultaneously, the memory processing device can synchronize the second result to the computing device via the cache coherence protocol. This achieves fast data transfer between the computing device and the memory processing device, saving memory space on the computing device and reducing the host processor overhead during the execution of the model processing task, thereby improving the task processing efficiency of the hardware computing device to a certain extent.

A method for processing an access request, a processing device, an electronic device and a non-transitory readable storage medium are disclosed. The first access request is used to acquire data in a processing device comprising a multi-level buffer memory. The method for processing an access request comprises: in response to the current level of the buffer memory receiving an access request, determining a priority level corresponding to the first access request; and based on the priority level corresponding to the first access request, determining the order in which the buffer memory processes the first access request or a second access request.

Embodiments of this application provide a memory processing method, an electronic device, and a readable storage medium. In the method, in a scenario in which an application program and a hardware device share a first physical memory, when the application program is switched to a background, the application program sends a first command to a memory processing apparatus, where the first command indicates to release the first physical memory of the application program; and the memory processing apparatus releases the first physical memory in response to the first command. In embodiments of this application, when the application program is switched to the background, and temporarily does not need to use the first physical memory, the application program may actively request to release the first physical memory, to increase an available memory of an electronic device.

A storage array for centralized logging is provided. The storage array for centralized logging includes one or more servers and a near memory processing NMP module. The one or more servers are configured to host one or more allocation units allocated to a logical volume. The NMP module is configured for one or more allocation units, and the NMP module is configured to record and update a state of a respective allocation unit in a reserved area of the respective allocation unit. The state includes a virtual offset of the respective allocation unit within a virtual log and a range of valid data in the respective allocation unit, and the NMP module is configured to return the allocation unit state in response to a command from one of one or more client devices.

This invention provides a semiconductor device structure and manufacturing method. The structure includes a semiconductor substrate having N-type and P-type device regions and corresponding gate structures; a dielectric barrier layer is located on the semiconductor substrate and P-type gate structure in the P-type device region; a stress layer is located on the semiconductor substrate and N-type gate structure in the N-type device region, and is also located on the dielectric barrier layer in the P-type device region. This invention introduces a dielectric barrier layer in a full-coverage stress memory process, subjecting the N-type device to high tensile stress to improve performance, while simultaneously reducing the tensile stress on the P-type device to avoid performance degradation. This approach can significantly reduce the lower limit of SRAM operating voltage, improve static noise margin and write margin, and the process is simple and highly compatible.

The utility model discloses a storage module clamp for double-sided gluing and a double-sided gluing device, and relates to the technical field of protective storage processing equipment. The storage module clamp comprises a clamp body. A first space used for clamping and positioning a main body part of the storage module, a second space used for clamping a flat cable leading-out part led out from the main body part of the storage module, and dispensing grooves used for exposing the two sides of the flat cable leading-out part located at the leading-out position respectively are formed in the clamp body. The fixture can simultaneously fix the main body part and the flat cable leading-out part which are positioned on the two sides of the leading-out part, and can avoid the situation that bubbles are generated on a gluing layer due to the shaking of the flat cable leading-out part in the dispensing process, so that the waterproof performance of a product is guaranteed.

The invention provides a method for improving electric leakage of a semiconductor device with a dislocation structure, and the method comprises the steps: providing a substrate, and forming a gate structure on the substrate; after a first side wall is formed on the side face of the gate structure, LDD regions are formed in the substrate on the two sides of the first side wall; forming a germanium-silicon layer in the PMOS region of the substrate; forming a non-crystallization region in the NMOS region of the substrate; after a sacrificial layer is deposited in the NMOS region, an annealing process is implemented, so that the non-crystallization region is recrystallized and a dislocation structure is formed; after the sacrificial layer is removed, etching the NMOS region so as to remove part of the dislocation structure; epitaxially growing a silicon layer in the groove formed in the etching region, and re-forming a complete dislocation structure; after a second side wall is formed on the side surface of the first side wall, forming a source / drain region in the substrate on two sides of the second side wall; and after a stress memory process is implemented, forming a contact hole. The twin crystal defect generated by initially forming the dislocation structure can be eliminated, so that the formation of an electric leakage channel is inhibited, and the device performance is improved.