54 results about "Memory defects" patented technology

An integrated circuit and method for testing memory on the integrated circuit are provided. The integrated circuit has processing logic for performing data processing operations on data, and a plurality of memory units for storing data for access by the processing logic. Further, memory test logic is provided to perform a sequence of tests in order to seek to detect memory defects in the memory units. The memory test logic comprises a plurality of test wrapper units, each test wrapper unit associated with one of the memory units and being operable to execute tests on the associated memory unit, and a test controller for controlling performance of the sequence of tests by communicating with each of the test wrapper units to provide test data defining each test to be executed by that test wrapper unit. Further, a first communication link is provided for connecting each of the test wrapper units directly to the test controller, and a second communication link is provided for connecting each test wrapper unit in an ordered sequence with the test controller. When controlling performance of the sequence of tests, the test controller provides first test data via the first communication link and second test data via the second communication link. It has been found that such an approach provides a particularly efficient and flexible technique for performing BIST functions within the integrated circuit.

A method is provided for managing defects in a semiconductor memory system having a plurality of addressable locations. In the method, a first plurality of the addressable locations is allocated as in-use locations, and a second plurality of the addressable locations is allocated as spare locations. A plurality of sets of the in-use locations, wherein each of the sets is associated with a memory defect, is determined. At least one of the sets includes a different number of in-use locations than another of the sets. Each of the sets of the in-use locations is associated with at least one corresponding set of the spare locations. Each of a plurality of data requests that is associated with one of the sets of the in-use locations is directed to the at least one corresponding set of the spare locations.

A life parameter generator generates life parameters related to the life of a nonvolatile memory device by using parameters related to allowable capacity for memory defect and occurrence capacity for memory defect. The life parameters are stored in a life parameter storing block of a nonvolatile memory. An access device reads and displays the stored life parameters. Thus, the user can precisely know the life of the nonvolatile memory device or the moment when a device having a built in nonvolatile memory such as a portable audio becomes unusable.

A system and method for defect analysis of multi-level memory cell devices and embedded multi-level memory in system-on-chip integrated circuits are disclosed wherein a defect data set is input into the system. When a defect data set is received, an automated test engineering system running a memory test program analyzes the defect data set to generate one or more fail bit locations and one or more fail states of the memory. The multi-level memory defect analysis system and method then classify failed bits or patterns comprising a vertical fail pattern, whereby after being classified, each memory cell failure vertical fail pattern has three data attributes comprising fail type, a number of fail bits / states, and a sequence of the fail states. The vertical fail pattern may comprise a single fail state or multi-state fail. The multi-state fail may be a continuous-states fail, discontinuous-states fail, or all-state fail. The multi-level memory defect analysis system and method may additionally enable classification of failed bits or patterns comprising a lateral fail pattern. The lateral fail pattern may be a gradual fail pattern, periodic fail pattern, or random fail pattern.

A life parameter generator generates life parameters related to the life of a nonvolatile memory device by using parameters related to allowable capacity for memory defect and occurrence capacity for memory defect. The life parameters are stored in a life parameter storing block of a nonvolatile memory. An access device reads and displays the stored life parameters. Thus, the user can precisely know the life of the nonvolatile memory device or the moment when a device having a built in nonvolatile memory such as a portable audio becomes unusable.