9 results about "Memory defects" patented technology

The invention relates to the technical field of data storage, and discloses a method and system for optimizing test data collected by a memory chip based on machine learning, and the method comprises the steps: collecting original test data from a test platform of a to-be-tested memory chip; constructing a convolutional neural network model, learning a mapping relationship between test data features and memory defects through the convolutional neural network model, training the convolutional neural network model through the collected original test data, optimizing parameters of the convolutional neural network model according to a training result through a back propagation algorithm, and obtaining memory defects through the optimized parameters. The performance of the convolutional neural network model tends to be stable; converting a parameter vector output by the convolutional neural network model into a test vector executable by ATE; and taking the generated test vector as a new training sample, feeding back the new training sample to an original test data updating data set, and iteratively training and optimizing the convolutional neural network model. According to the invention, intelligentization of the test process is realized, and hidden defects sensitive to voltage and time sequence can be effectively captured.

A memory device includes a memory cell array including a plurality of memory cells, a word line defect detection circuit electrically connected to the memory cell array through a plurality of word lines, and control logic configured to control an input / output operation of the memory cell array. When a memory defect detection command is received from a memory controller, the word line defect detection circuit is configured to provide an input voltage to a selected word line among the plurality of word lines, and to generate a fail flag based on a difference between a voltage of the selected word line and a reference voltage. When a mode register read command is received from the memory controller, the control logic is configured to transmit the fail flag and a fail row address corresponding to the fail flag to the memory controller.

Intranasal neuropeptide Y (NPY) analogs having D-amino acids, such as [D26-His]-NPY are provided for early intervention to prevent or to treat, to reverse, or reduce symptoms of stress-related impairments such as PTSD, depression, substance abuse, and / or memory deficits following exposure to traumatic or surgical stress.

Systems and methods are provided for implementing improved memory defect management. Bad pages, referring to portions of memory affected by memory errors, are identified by an operating system (“OS”) of a computing system. A list of bad pages may be periodically uploaded to a cloud data storage. The OS may also send the list of bad pages to a basic input / output system (“BIOS”) for repair of some of the bad pages. A list of repaired bad pages or corresponding status information may be sent to the OS. In some examples, the list of bad pages is compared with the list of repaired bad pages and may be updated accordingly. The list of bad pages may be compared with a previously uploaded list of bad pages that has been received from the cloud data storage. One list may be updated with, or replaced by, the other list based on the comparison.

The application relates to the technical field of data storage, and discloses a method for optimizing test data collected by a memory chip based on machine learning and a system thereof, which comprises the following steps: collecting original test data from a test platform of a to-be-tested memory chip; constructing a convolutional neural network model, learning a mapping relationship between test data features and memory defects through the convolutional neural network model, training the convolutional neural network model through the collected original test data, optimizing parameters of the convolutional neural network model through a back propagation algorithm according to a training result until the performance of the convolutional neural network model tends to be stable; converting a parameter vector output by the convolutional neural network model into an executable test vector of ATE; feeding the generated test vector as a new training sample back to an original test data update data set to iteratively train and optimize the convolutional neural network model. The application realizes the intelligentization of a test process and can effectively capture implicit defects sensitive to voltage and timing.

Systems and methods are provided for implementing improved memory defect management. Bad pages, referring to portions of memory affected by memory errors, are identified by an operating system (“OS”) of a computing system. A list of bad pages may be periodically uploaded to a cloud data storage. The OS may also send the list of bad pages to a basic input / output system (“BIOS”) for repair of some of the bad pages. A list of repaired bad pages or corresponding status information may be sent to the OS. In some examples, the list of bad pages is compared with the list of repaired bad pages and may be updated accordingly. The list of bad pages may be compared with a previously uploaded list of bad pages that has been received from the cloud data storage. One list may be updated with, or replaced by, the other list based on the comparison.

Disclosed embodiments include systems and methods for tracking defective memory using a shared memory defect list. Embodiments include firmware that identifies a memory buffer to store a list that includes an entry identifying a portion of memory as defective. The firmware sends an identification of the memory buffer to an operating system. The operating system reads the list from the memory and identifies the portion of defective memory based on the list. The operating system further manages memory locations used based on the identified portion of defective memory and avoids using the portion of defective memory. The firmware persists the contents of the memory to a non-volatile storage prior to shutting down the computer system.

The application provides a memory defect static detection method based on a type region model, first, function call graphs and control flow graphs of a program to be detected are obtained through front-end processing; then, a type region model is constructed based on the function call graphs and the control flow graphs, static analysis is carried out, and the model and the program state are updated after the analysis; and then, according to defect behaviors that can occur at a current program point and program state information carried by the static analysis, a detection process of a certain defect type is entered. Through the memory defect detection method based on the type region model, the application can accurately describe the state of the program, ensure the correctness of data flow information at most program points, can analyze deeper reasons for the occurrence of memory defects in detail, and designs corresponding defect detection rules to ensure sufficient detection of the defects and reduce false negatives and false positives.