18 results about "Shadow memory" patented technology

The invention discloses an operating system containerization kernel compatibility method based on shadow structure mapping, which comprises the following steps of: constructing a multi-dimensional mapping rule base by analyzing the difference of data structures between a container system and a standard system, and creating a shadow structure comprising a data area, a metadata area and an expansion area when the container system runs on a host system; the host system allocates a shadow memory space and a memory pool, establishes mapping between a shadow structure and a physical memory page and bidirectional mapping between the shadow structure and a host structure, intercepts system call of a container application, obtains a target structure and allocates a shadow structure and a host structure memory, and sends the shadow structure and the host structure memory to the host system; according to the method, conversion from the target structure to the host structure is completed according to the multi-dimensional mapping rule base, the host machine completes calling through the host structure, then the calling result is reversely converted into the target structure and returned to the container application, and seamless compatibility of the container system and the host system is achieved under the condition that a user mode program of the container system is not modified.

The invention belongs to the field of industrial control and computer data security, and particularly relates to a millisecond-level power failure data protection system for an industrial control panel. The invention discloses a millisecond power failure data protection system for an industrial control panel. The millisecond power failure data protection system comprises a core processing component, a real-time synchronous shadow memory component, a bus voltage monitoring component, a pre-entropy reduction logic control component, a nonvolatile storage component and a flight control bus arbitration component. The bus voltage monitoring assembly monitors a voltage drop trend and performs early warning, the pre-entropy reduction logic control assembly calculates a minimum data survival set according to energy entropy, the real-time synchronous shadow memory assembly constructs a synchronous shadow control domain and atomizes data, and the flight control bus arbitration assembly compulsively takes over a bus and freezes processor access at the moment of power failure. Atomized writing of data into the nonvolatile storage component is guaranteed. According to the invention, zero-delay data protection and millisecond-level hot start recovery at the moment of power failure are realized, and the data security and reliability of the industrial control equipment in a severe environment are enhanced.

The application discloses an operating system containerization kernel compatibility method based on shadow structure mapping, constructs a multi-dimensional mapping rule library by analyzing the difference between the data structure of a container system and a standard system, creates a shadow structure containing a data area, a metadata area and an extension area when the container system runs on a host system, allocates shadow memory space and a memory pool by the host system, establishes the mapping between the shadow structure and a physical memory page and the bidirectional mapping between the shadow structure and a host structure, intercepts the system call of a container application by the host system, obtains a target structure and allocates the shadow structure and the host structure memory, completes the conversion of the target structure to the host structure according to the multi-dimensional mapping rule library, completes the call by the host computer using the host structure, reversely converts the call result into the target structure and returns the call result to the container application, and realizes the seamless compatibility between the container system and the host system without modifying the user state program of the container system.

The invention provides a binary instrumentation method for an LL / SC lock instruction. The binary instrumentation method comprises the steps that S1, a DBI tool is prepared in advance and started; s2, loading an LL / SC atomic operation instruction sequence and distributing a corresponding memory; s3, decoding and translating a machine code corresponding to the LL / SC atomic operation instruction sequence by the DBI tool, and converting the machine code into an IR intermediate expression; s4, shadow memory instrumentation is carried out based on IR intermediate expression; and S5, converting the IR intermediate expression after instrumentation into a target machine code, and running in a simulation environment of a DBI tool to obtain execution information of the LL / SC atomic operation instruction sequence. According to the method, correct translation and code instrumentation can be carried out on the multi-thread application containing the LL / SC, correct translation of the LL / SC instruction pair in the binary instrumentation framework is ensured, and correctness and atomicity of modification of the translated instruction to the sharing state in the competition state are ensured.

An apparatus has a data memory region with multiple data symbols and inaccessible zones, a first inaccessible zone placed before each data symbol and a second inaccessible zone placed after each data symbol. The apparatus also has a shadow memory region corresponding to the data memory region. The shadow memory region includes multiple data elements. Each data element corresponds to one of the data symbols or inaccessible zones and indicates an accessibility state of the corresponding data symbol or inaccessible zone. The apparatus includes an address sanitizer hardware block within a processing core and coupled to the shadow memory region. The address sanitizer hardware block checks a selected data element of the shadow memory region, corresponding to a selected data symbol or inaccessible zone being accessed, to determine the accessibility state of the selected data symbol or inaccessible zone, prior to accessing the selected data symbol or inaccessible zone.

The invention relates to the technical field of game data processing, in particular to a dynamic adjustment system for a three-elimination game layout, which comprises a matrix state acquisition module, a virtual rehearsal simulation module, a virtual rehearsal simulation module, a virtual rehearsal simulation module, a virtual rehearsal simulation module and a virtual rehearsal simulation module, and the constraint reverse solving module calculates target element features by utilizing a reverse deduction algorithm based on dead bureau or abnormal linkage feedback generated by simulation, and the layout data synchronization module writes correction data into a pipeline. According to the method, a shadow memory rehearsal mechanism and reverse deduction logic based on result guidance are introduced, so that the problems of no solution dead bureau of a layout and unexpected automatic chain elimination caused by a random generation algorithm in the prior art are thoroughly solved, logic leakproofness is guaranteed, and meanwhile, dynamic regulation and control of rhythm elimination and level difficulty are realized; and the system response speed and the user interaction experience under complex logic judgment are greatly improved.

The embodiment of the invention provides a memory security violation detection method and device, computer equipment and a storage medium. A magic number is inserted in advance for a red area and a released memory area in a memory allocated by each application program. The method comprises the following steps: determining whether a magic number is stored in a target memory object of a specified application program or not; the target memory object is a section of continuous memory in which memory security violation may occur in a heap region, a stack region or a global region; under the condition that the magic number is stored in the target memory object, determining whether the target memory object is accessible or not; and under the condition that the target memory object is inaccessible, determining that the memory security violation exists. The shadow memory class is not directly queried to determine whether the memory security is violated, but whether the magic number is stored in the target memory object is determined firstly, and whether the target memory object is accessible is determined only when the magic number exists, so that the extra runtime overhead during the running of the specified application program can be reduced, and the memory security of the specified application program is improved. And the resource utilization efficiency is improved.

An apparatus has a data memory region with multiple data symbols and inaccessible zones, a first inaccessible zone placed before each data symbol and a second inaccessible zone placed after each data symbol. The apparatus also has a shadow memory region corresponding to the data memory region. The shadow memory region includes multiple data elements. Each data element corresponds to one of the data symbols or inaccessible zones and indicates an accessibility state of the corresponding data symbol or inaccessible zone. The apparatus includes an address sanitizer hardware block within a processing core and coupled to the shadow memory region. The address sanitizer hardware block checks a selected data element of the shadow memory region, corresponding to a selected data symbol or inaccessible zone being accessed, to determine the accessibility state of the selected data symbol or inaccessible zone, prior to accessing the selected data symbol or inaccessible zone.

The application discloses a dynamic taint analysis method and system for firmware full-system simulation, and the method comprises the following steps: S1, after starting the taint tracking function, when receiving the data to be analyzed, the physical memory address of the current data in the virtual machine is found, and the specified part is marked as taint in the shadow memory; S2, during the execution cycle of the taint marked data to be analyzed, the TCG instruction of the client instruction disassembled is instrumented, and the preset taint propagation instruction is inserted before each instruction to manipulate the propagation of taint information, so that the TCG instruction after being instrumented realizes the flow of taint information during the interpretation execution process; S3, the taint detection module detects the taint information in real time, and when it is detected that the register or shadow memory storing the key information is marked as taint, the taint propagation is ended and the pollution state information is output. The application can track taint information in real time and accurately during firmware full-system simulation.

The invention provides a multi-Sanitizer binary system detection system and method for a vehicle-mounted closed source system kernel, and the system comprises a function level hook which is used for detecting whether a TB start is an entrance of a concerned function or not in a TB translation stage, inserting an entry hook when the TB start is hit, recording a return address and a stack pointer, and judging function return through the subsequent TB start to trigger post-processing; the composite shadow memory is used for representing the 8B tested memory by a preset digit; mapping is established during distribution, a redzone and an uninitialized mark are set, the state is set to be in a released state during release, uninitialized is written and cleared, and violation is reported when an abnormal state is hit by access; and the process-level selective Sanitize is used for tracking a context switching entry of the kernel and maintaining process information and a Sanitizer bitmap of each CPU (Central Processing Unit). According to the invention, the technical problems of closed source, non-changeable kernel, lack of effective Oracle, single Sanitizer isolation, performance and adaptability are solved.

The invention particularly relates to a monitoring method for memory anomaly detection, a terminal and a storage medium, and the monitoring method comprises the steps: creating a running memory of an object, and creating a shadow memory of the running memory; before the running memory is called, available information of a shadow memory corresponding to the running memory is obtained, and if the available information is set to be unavailable, a warning indicating that memory abnormity exists in an object corresponding to the available information is thrown out. The shadow memory and the new memory release program are configured for the running memory, when the object is not released by the memory release program, the abnormity of the object can be quickly warned by combining the information stored by the shadow program, and the positioning efficiency and the positioning precision of memory abnormity detection are improved.

A present invention embodiment performs memory management and shadow queueing in a hypervisor environment. A queue is created in a hypervisor system that includes a host and a guest, wherein the queue is created in response to the guest issuing an I / O instruction, and wherein creating the queue comprises providing guest memory tables and corresponding shadow tables in the host that are accessed by an adapter. Data of the I / O instruction is stored to the guest memory tables, which are synchronized with the shadow memory tables, wherein the synchronizing comprises translating guest memory addresses into host memory addresses and pinning the guest memory addresses. A host unpin structure is provided with a copy of translated and pinned host memory addresses. In response to the adapter executing the I / O instruction, the host unpin structure is utilized, by the host, to locate and unpin the translated and pinned host memory addresses.

A spiking neuron reinforcement circuit and method address the existing flaw in spiking neurons, which are susceptible to computational errors due to single-particle effects, and effectively improve the spatial adaptability of spiking neurons. This method utilizes configuration information and model parameters to achieve the spiking neurons and neuron discharge pulse signals required by spiking neural networks. Furthermore, the method uses an ECC codec module to perform error correction and fault tolerance on the configuration information and model parameters. Furthermore, the method uses a shadow memory (or register bank) to back up and fault-tolerant the configuration information and model parameters.

Methods, systems, and apparatus for a system-level repair sharing serial interface to function with external programs and software for the repairing of memory. One of the methods includes assigning shadow memories that are read through the use of a logical comparator, a fault detection system of sticky flops, and a fault reinjection system that accepts input from both the main memory scan out and the output of the logical comparator.

Systems and methods for efficient peripheral device software request queue shadowing for virtual machines can include creating a virtual machine and assigning a peripheral device to it. They can also include assigning, to the peripheral device, a first process address space identifier (PASID) associated with a shadow memory buffer and a second PASID associated with a device data buffer. They can further include causing a host input / output memory management unit (IOMMU) to identify a software request in the shadow memory buffer, and fetching, from the shadow memory buffer, the software request and a guest memory address of data requested to be accessed. They can also include, causing the host IOMMU to identify the data in the device data buffer, and transmitting the data, from the guest memory, to the peripheral device.

The invention provides a memory border crossing detection method and device, electronic equipment and a storage medium, and relates to the technical field of computers. The method comprises the following steps: when a running memory is allocated to a target program, configuring a shadow memory corresponding to the running memory; determining all virtual memory pages mapped by the virtual address range of the running memory and an in-page access range of each virtual memory page; based on the in-page access range, respectively writing in-page access range data corresponding to each virtual memory page in the shadow memory; and before the memory access instruction in the target program is executed, performing border crossing judgment on an access address in the memory access instruction according to the in-page access range data. According to the scheme, the shadow memory can be configured for the program, the in-page access range data is written into the shadow memory, and border crossing judgment is performed based on the in-page access range data before the memory access instruction is executed, so that the detection precision of memory border crossing detection is improved.

The application discloses a scheduling system and method of an aircraft avionics network and the network, and relates to the technical field of avionics communication networks. The system comprises a switching node supporting a time-sensitive network; a flight control computer connected to the switching node and used for generating and sending a flight state message; a network management unit connected to the switching node, used for receiving the message and making a stability decision, and generating a switching instruction when a stable switching condition is met; and at least one scheduling execution unit used for responding to the switching instruction and executing a period boundary locking algorithm to switch to a gating list corresponding to a target flight state within a protection zone before the end of a current scheduling period. A shadow memory is arranged in the scheduling execution unit and pre-stores multiple sets of gating lists corresponding to respective flight states. The application realizes dynamic adaptation of avionics network resources through a flight state driven dynamic scheduling mechanism, and improves communication accuracy and scheduling reliability in a flight task.

The present invention provides a memory compression method for Shadow Memory memory leak detection mechanism, belonging to the field of computer applications. In order to solve the problem of large memory overhead caused by small object size, the method of the present invention uses a mechanism of fuzzy representation of object information - object fusion, to perform Shadow Memory memory compression. For objects with a minimum size of k bytes, if the pointer difference between two adjacent objects does not exceed 2k bytes, the two objects share an object identification unit; at the same time, in order to eliminate the object omissions caused by this, two solutions are provided: outputting supplementary information, and randomly overwriting and combining the output results of multiple leak detection runs to solve the object omissions. The method of the present invention makes an appropriate trade-off between the accuracy of leak detection and memory load, so that the memory consumption of the leak detection module is reduced by half, and the workload of checking leaking objects is also reduced, thereby accelerating the efficiency of leak detection.