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Semiconductor memory device

Inactive Publication Date: 2016-04-21
ROHM CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention aims to provide a semiconductor memory device that saves power, operates quickly, and has better yield during active periods.

Problems solved by technology

If, for the sake of discussion, a volatile memory (e.g., SRAM (static random-access memory)) is used as a data buffer in an application as mentioned above, the leak current through it may greatly affect the total electric power consumption of the system.
FeRAM, however, is not quite satisfactory in driving speed and electric power consumption during an active period, and in durability.
Inconveniently, however, compared with SRAM having a 6T structure, ferroelectric shadow memory has the following shortcomings: (1) high electric power consumption during an active period; (2) slow operation speed during an active period; and (3) difficulty detecting defects in ferroelectric capacitors due to production variations.

Method used

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  • Semiconductor memory device
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Examples

Experimental program
Comparison scheme
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first embodiment

[0088]Next, a description will be given of a bit line non-precharge method, in which the bit line and the inverted bit line are not precharged during a read / write operation.

[0089]FIG. 4 is a diagram illustrating the necessity for bit line precharging in an SRAM memory cell having a 6T structure. As shown there, a plurality of SRAM memory cells 11-1 and 11-2 belonging to the same row are all connected to a single word line WL. On the other hand, a plurality of SRAM memory cells 11-1 and 11-2 belonging to different columns are respectively connected to corresponding bit lines BL1 and BL2 and to corresponding inverted bit lines XBL1 and XBL2.

[0090]In a read / write operation in the SRAM memory cell 11-1, the word line WL is raised to high level. As a result, the SRAM memory cell 11-1 that is a target of the read / write operation becomes connected to the corresponding bit line BL1 and inverted bit line XBL1. Here, the word line WL is connected also to the SRAM memory cell 11-2 that is not ...

second embodiment

[0111]Next, a description will be given of a plate line charge share method in which electric charge is shared between plate lines PL1 and PL2 that are sequentially driven in a store / recall operation.

[0112]FIG. 9 is a diagram showing one example of configuration for achieving the plate line charge share method. The semiconductor memory device 100 of this configuration example includes, as described previously, a plurality of memory cells 11 arrayed in a matrix, plate lines PL1(a, b, . . . ) and PL2(a, b, . . . ) connected to the plurality of memory cells 11 respectively, a plate line driver 40 for driving the plate lines PL1(a, b, . . . ) and PL2(a, b, . . . ) individually, and a memory controller 2 for controlling access to the plurality of memory cells 11.

[0113]The semiconductor memory device 100 of this configuration example further includes a plurality of transmission gates SW1(ab, bc, . . . ) and SW2(ab, bc, . . . ) commented between adjacent plate lines. Specifically, a transm...

third embodiment

[0127]As shown in FIG. 2 previously referred to, in a ferroelectric shadow memory having a 6T-4C structure, internal nodes Node1 and Node2 are connected to ferroelectric capacitors FC1 to FC4 with a high capacitance. Thus, with a ferroelectric shadow memory, data writing during an active period requires longer time than with an SRAM having a 6T structure. As a solution to this problem, a description will be given below of a word line boost method in which the potential on a word line WL is raised in a write operation.

[0128]FIG. 12 is a circuit diagram showing one example of the configuration of the word line driver 20. The word line driver 20 of this configuration example includes P-channel type field-effect transistors 21 and 22, an N-channel type field-effect transistor 23, an inverter 24, and a capacitor element 25.

[0129]The source of the transistor 21 is connected to a supply voltage node. The drain of the transistor 21 is connected to the source of the transistor 22. The drains...

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Abstract

Proposed as a configuration, a controlling method, and a testing method for a ferroelectric shadow memory are (1) a bit line non-precharge method, in which no precharging of a bit line is performed during a read / write operation; (2) a plate line charge share method, in which electric charge is shared between plate lines that are driven sequentially during store / recall operation; (3) a word line boost method, in which the potential on a word line is raised during a write operation; (4) a plate line driver boost method, in which the driving capacity of a plate line driver is raised during a store / recall operation; and (5) a testing method for detecting a defect in a ferroelectric capacitor by arbitrarily setting a potential on a bit line from outside a chip.

Description

[0001]This application is based on Japanese Patent Application No. 2014-212787 filed on Oct. 17, 2014, the contents of which are hereby incorporated by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to semiconductor memory devices.[0004]2. Description of Related Art[0005]Today, nonvolatile memories are widely used in system-on-chip (SoC) devices incorporated in a variety of applications. In particular, in applications with low active factors (such as in sensor networks and in living body monitoring), tight restrictions are imposed on electric power consumption during a standby period with a view to reducing battery capacity and system module size.[0006]If, for the sake of discussion, a volatile memory (e.g., SRAM (static random-access memory)) is used as a data buffer in an application as mentioned above, the leak current through it may greatly affect the total electric power consumption of the system. On the other hand, when ...

Claims

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Application Information

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IPC IPC(8): G11C11/22G11C29/08
CPCG11C11/2259G11C29/08G11C11/221G11C29/50G11C14/0072
Inventor IZUMI, SHINTARONAKAGAWA, TOMOKIKAWAGUCHIYOSHIMOTO, MASAHIKO
Owner ROHM CO LTD
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