5results about How to "Reduce memory access" patented technology

The invention discloses a global nerve drawing method and system based on a programmable rasterization engine, and belongs to the technical field of computer graphics, and the method comprises the steps: at the programmable rasterization engine, analyzing a rasterization descriptor according to a rasterization instruction, and extracting vector microoperation and control parameters; maintaining a task state machine according to the parameters and distributing a control signal, selecting an execution entry from a vector kernel table according to the control signal, and instantiating an operation into a parallel vector thread; in a vector thread execution process, tracking data dependence of a vector register and a synchronization state of a direct memory access unit, executing vector loading / storage operation so as to carry data between the register and an on-chip shared memory according to the data dependence and the synchronization state, and dynamically scheduling vector micro-operation to an execution component so as to complete rasterization calculation; and outputting a result to the neural rendering network to complete global neural rendering. According to the method, the multi-representation neural rendering load can be uniformly and efficiently supported on the AI accelerator, the memory access overhead is remarkably reduced, and the calculation efficiency is improved.

The invention provides a multi-dimensional self-adaptive large model inference engine method and system, and relates to the technical field of artificial intelligence, and the method comprises the steps: collecting hardware identification information of calculation hardware, and calling a hardware fingerprint database for matching to generate a hardware type result and a hardware characteristic parameter; constructing a hardware abstraction layer, loading a hardware abstraction driving plug-in according to a hardware type result, and virtualizing computing hardware into a unified logic computing power unit through a hardware abstraction interface; when a large model reasoning task is triggered, dynamically routing to a back-end executor according to a hardware type result by querying a back-end registry; on the basis of hardware characteristic parameters and a hardware abstract interface, a hardware compiling tool chain is called through a rear-end executor, graph optimization and operator fusion are executed on a large model calculation graph, and therefore self-adaptive deployment and efficient reasoning of a large model on heterogeneous hardware can be achieved; the problems that in the prior art, heterogeneous hardware is insufficient in compatibility, configuration is tedious and rigid, and compilation optimization barriers and performance losses are caused during model cross-platform migration are solved.

This application provides a GPU-based sparse matrix-vector multiplication optimization method and apparatus for large-scale computing. The method includes rearranging and reorganizing the sparse matrix to make the distribution of non-zero elements in adjacent columns of the rearranged sparse matrix more similar; dividing the non-zero elements in each row of the sorted sparse matrix into several slices, placing the slices into containers that satisfy constraints, namely, the starting column index of the newly added slice is consecutive to the column indices of other existing slices; each container corresponds to a synchronous execution unit, and several synchronous threads perform the multiplication and accumulation of non-zero elements with the corresponding components of the input vector. Thus, matrix rearrangement makes it more likely that a synchronous execution unit will process data from the same row; by dividing non-zero elements with the same row index and consecutive column indices into slices and placing them into containers, the continuity of data processed by the synchronous execution unit in the column direction reduces non-merged memory accesses and enhances data reuse capabilities.

The invention discloses a low-delay streaming voice wake-up method and device for an embedded terminal, is applied to the technical field of data processing, and adopts a GRU as a backbone architecture for the requirements of low power consumption and high real-time performance of voice wake-up of the embedded terminal. The original audio is segmented and reconstructed through time domain lightweight preprocessing, and the FFT overhead is eliminated through linear layer mapping; building a multi-layer GRU full-causal streaming coding network, wherein no sliding window cache exists, and the memory bandwidth occupies O (1); outputting Token probability distribution containing Blank through a CTCLoss training module, and directionally extracting a target Token probability; constructing a target index sequence based on the target wake-up word and a CTC protocol, and setting three types of state transition rules to generate anti-interference decoding information; and a non-Top-K pruning decoding mechanism is adopted, an attenuation factor and threshold judgment is combined, a judgment result with constant calculation complexity and low false and missing wakeup is generated, and subsequent interaction is triggered if the judgment result succeeds.

The application provides a point cloud data processing method, system and device based on spatial serialization, the method comprising: sorting point cloud data by using a six-way standard sequence sorting method to obtain point cloud data sequences; dynamically and automatically selecting focal point blocks in the sequenced data according to a view cone and screen projection error, and dynamically adjusting the LOD level of each focal point block to obtain sequenced LOD data; after the sequenced LOD data is managed by VIBO block management, performing triangle optimization reconstruction; using a UV space remapping algorithm, performing patch and texture alignment processing on the point cloud surface after triangle optimization reconstruction, and performing multi-format texture packing to complete rendering output. The application reduces unnecessary calculation and memory access through dynamic adjustment of the LOD of the focal point block and VIBO block caching. Through dynamic LOD adjustment and optimized triangle reconstruction technology, combined with efficient texture packing and decompression, the rendering frame rate can be significantly improved while details are maintained.