This invention discloses a real-time multi-
exposure HDR
image processing system based on FPGA, comprising: a DDR3
image storage control module, integrated within the FPGA, communicating with an external DDR3
chip via the AXI4
bus protocol, supporting high-speed storage and parallel reading of 8-channel multi-
exposure images, and outputting synchronized multi-
exposure image data and valid frame, line, and data signals; a multi-exposure HDR fusion module, connected to the output of the DDR3
image storage control module, employing a 6-stage hardware pipeline architecture to achieve pixel-level weighted fusion of 8-channel multi-exposure images, outputting a 24-bit RGB format HDR
fusion image; and a Reinhard
tone mapping module, connected to the output of the multi-exposure HDR fusion module, implementing
dynamic range compression from HDR to LDR images based on an optimized Reinhard
algorithm, outputting a 24-bit RGB format LDR image that meets the requirements of display devices. This invention achieves real-
time processing of multi-exposure HDR images throughout the entire process through the integrated and synchronized optimization of these three modules.