4results about How to "Lower memory access latency" patented technology

The invention discloses a global nerve drawing method and system based on a programmable rasterization engine, and belongs to the technical field of computer graphics, and the method comprises the steps: at the programmable rasterization engine, analyzing a rasterization descriptor according to a rasterization instruction, and extracting vector microoperation and control parameters; maintaining a task state machine according to the parameters and distributing a control signal, selecting an execution entry from a vector kernel table according to the control signal, and instantiating an operation into a parallel vector thread; in a vector thread execution process, tracking data dependence of a vector register and a synchronization state of a direct memory access unit, executing vector loading / storage operation so as to carry data between the register and an on-chip shared memory according to the data dependence and the synchronization state, and dynamically scheduling vector micro-operation to an execution component so as to complete rasterization calculation; and outputting a result to the neural rendering network to complete global neural rendering. According to the method, the multi-representation neural rendering load can be uniformly and efficiently supported on the AI accelerator, the memory access overhead is remarkably reduced, and the calculation efficiency is improved.

The application discloses a batch processing matrix multiplication optimization implementation method and system for a heterogeneous processor, and the method comprises the following steps: in step S1, a CPU allocates space for a matrix on a shared DDR memory through an hthread_malloc function; in step S2, the CPU calculates decision parameters through a decision algorithm, wherein the decision parameters comprise a matrix block size parameter and an m_batch size parameter; and in step S3, a DSP function is started based on the decision parameters. The application has the following beneficial effects: a high-efficiency batch processing matrix multiplication (BGEMM) algorithm is implemented on a DSP, and the BGEMM algorithm can effectively accelerate multi-field applications including deep learning; the memory access delay of a DSP calculation unit is reduced, the calculation speed is improved, and the calculation efficiency of GEMM is improved.

This application provides a hardware passthrough method, apparatus, device, and storage medium for virtual machines. The hardware passthrough method includes: obtaining an attribute description file for a newly created virtual machine; the attribute description file describes the resource requirements of the newly created virtual machine, including PCIe interface parameters and memory allocation specifications; based on a PCIe device topology mapping table, determining the target hardware resources that conform to the PCIe interface parameters and their corresponding target NUMA nodes; within the target NUMA node, allocating memory resources of corresponding capacity to the newly created virtual machine according to the memory allocation specifications; and binding and mapping the target hardware resources to the newly created virtual machine through the IOMMU hardware virtualization mechanism, thereby achieving hardware passthrough. By parsing the virtual machine resource requirements and matching them according to precise hardware topology and NUMA node information, the collaborative allocation of PCIe devices and memory resources is dynamically and efficiently achieved, significantly improving the utilization rate of heterogeneous computing resources and reducing energy consumption and maintenance costs.

This invention discloses a data prefetching method, product, device, and medium based on multiple memory access patterns, relating to the field of computer architecture technology. The method includes: monitoring for L2 cache memory access miss events in the processor; if the miss status register hits the event, splitting the miss address to obtain the base address of the spatial region and the offset address within the region. When the program counter pattern training table hits the base address, stride and spatiotemporal pattern training is performed on the offset address to obtain a fixed stride, space / time related access pattern. Valid memory access patterns are filtered by confidence level and stored in the corresponding LLC pattern table, with an index recorded in the prefetch pattern record table. Subsequently, based on the memory access miss event and index information, the target pattern is read from the corresponding pattern table to calculate the prefetch address, generate a request, and execute the prefetch. Through this scheme, it is possible to adapt to multiple scenarios and accurately identify memory access patterns for more precise data prefetching.