10results about How to "Lower memory access latency" patented technology

The embodiment of the invention provides a chip, a memory access method and device, a consistency management module and computer equipment, and the chip comprises an address transmission network which is used for routing a memory access address to the consistency management module; the network-on-chip is used for routing the memory access request of the CPU core to the consistency management module; the routing speed of the address transmission network is higher than that of the network-on-chip; the consistency management module is used for acquiring a predictive memory access request, and the predictive memory access request is generated based on the memory access address; transmitting the predictive memory access request to a memory control module, and obtaining predictive data prefetched from a memory by the memory control module based on the predictive memory access request; storing the prediction data and the corresponding memory access address; judging whether memory access data requested by the memory access request is prefetched or not; and if yes, taking the stored prediction data of the memory access address corresponding to the memory access request as memory access data, and feeding back the memory access data to the CPU core through the network-on-chip. According to the embodiment of the invention, the memory access delay of the CPU core can be reduced.

The invention discloses an asynchronous prefetching system based on 3D stacking. The asynchronous prefetching system comprises an on-chip structure and at least one layer of off-chip structure interconnected with the on-chip structure. The on-chip structure comprises at least one computing core, at least one asynchronous prefetching module corresponding to the computing core and an on-chip prefetching queue, the off-chip structure comprises at least one off-chip prefetching queue, and the depth of the off-chip prefetching queue is greater than that of the on-chip prefetching queue. The on-chip prefetching queue and the off-chip prefetching queue are connected in series to form an asynchronous prefetching assembly line; the asynchronous prefetching module is used for prefetching data from a global memory to the tail of an off-chip prefetching queue based on an asynchronous prefetching assembly line, transmitting the data from the head of the off-chip prefetching queue to the tail of an on-chip prefetching queue, and providing required data for a computing core of the on-chip structure. The overhead of the computing core during data access processing is reduced, and the memory access delay is reduced.

The invention discloses a global nerve drawing method and system based on a programmable rasterization engine, and belongs to the technical field of computer graphics, and the method comprises the steps: at the programmable rasterization engine, analyzing a rasterization descriptor according to a rasterization instruction, and extracting vector microoperation and control parameters; maintaining a task state machine according to the parameters and distributing a control signal, selecting an execution entry from a vector kernel table according to the control signal, and instantiating an operation into a parallel vector thread; in a vector thread execution process, tracking data dependence of a vector register and a synchronization state of a direct memory access unit, executing vector loading / storage operation so as to carry data between the register and an on-chip shared memory according to the data dependence and the synchronization state, and dynamically scheduling vector micro-operation to an execution component so as to complete rasterization calculation; and outputting a result to the neural rendering network to complete global neural rendering. According to the method, the multi-representation neural rendering load can be uniformly and efficiently supported on the AI accelerator, the memory access overhead is remarkably reduced, and the calculation efficiency is improved.

The application discloses a batch processing matrix multiplication optimization implementation method and system for a heterogeneous processor, and the method comprises the following steps: in step S1, a CPU allocates space for a matrix on a shared DDR memory through an hthread_malloc function; in step S2, the CPU calculates decision parameters through a decision algorithm, wherein the decision parameters comprise a matrix block size parameter and an m_batch size parameter; and in step S3, a DSP function is started based on the decision parameters. The application has the following beneficial effects: a high-efficiency batch processing matrix multiplication (BGEMM) algorithm is implemented on a DSP, and the BGEMM algorithm can effectively accelerate multi-field applications including deep learning; the memory access delay of a DSP calculation unit is reduced, the calculation speed is improved, and the calculation efficiency of GEMM is improved.

This application provides a hardware passthrough method, apparatus, device, and storage medium for virtual machines. The hardware passthrough method includes: obtaining an attribute description file for a newly created virtual machine; the attribute description file describes the resource requirements of the newly created virtual machine, including PCIe interface parameters and memory allocation specifications; based on a PCIe device topology mapping table, determining the target hardware resources that conform to the PCIe interface parameters and their corresponding target NUMA nodes; within the target NUMA node, allocating memory resources of corresponding capacity to the newly created virtual machine according to the memory allocation specifications; and binding and mapping the target hardware resources to the newly created virtual machine through the IOMMU hardware virtualization mechanism, thereby achieving hardware passthrough. By parsing the virtual machine resource requirements and matching them according to precise hardware topology and NUMA node information, the collaborative allocation of PCIe devices and memory resources is dynamically and efficiently achieved, significantly improving the utilization rate of heterogeneous computing resources and reducing energy consumption and maintenance costs.

The application discloses a communication resource scheduling method and system based on GPU parallel computing, aiming at the eMBB and URLLC service coexistence scene, first, the mean and variance of service communication are utilized to construct a joint opportunity constraint model to represent service demand in an uncertain environment; then, a large-scale parallel sorting is executed through a GPU kernel function to identify a promising resource allocation space and realize search space dimension reduction; after a plurality of allocation instances are generated by sampling, resource block reduction, analytical power allocation based on a water injection algorithm and cross-time domain risk shaping calculation are synchronously executed by using the kernel function; finally, a global optimal scheduling scheme is screened out according to the minimum rate loss minimization principle of eMBB through the parallel reduction logic of the kernel function. Under the premise of guaranteeing the extremely low time delay and high reliability of URLLC, the rate loss of eMBB service is significantly reduced, and the decision delay can meet the real-time requirement.

The present invention discloses a compilation optimization method based on a cache write hint mechanism, which automatically identifies instruction sequences for writing to continuous main memory, and optimizes the memory access behaviors of these instruction sequences through instruction insertion, including the following steps: S1: identifying all write operations in the code and marking them through insertion; S2: determining the access continuity of the data units of the write operations identified in S1, and updating the cachesc instruction parameters if the continuity requirements are met; S3: writing operation boundary processing. The present invention can reduce the interference of cumbersome storage management on the code production process, further reduce memory access delay, and improve storage system performance.

This invention discloses a data prefetching method, product, device, and medium based on multiple memory access patterns, relating to the field of computer architecture technology. The method includes: monitoring for L2 cache memory access miss events in the processor; if the miss status register hits the event, splitting the miss address to obtain the base address of the spatial region and the offset address within the region. When the program counter pattern training table hits the base address, stride and spatiotemporal pattern training is performed on the offset address to obtain a fixed stride, space / time related access pattern. Valid memory access patterns are filtered by confidence level and stored in the corresponding LLC pattern table, with an index recorded in the prefetch pattern record table. Subsequently, based on the memory access miss event and index information, the target pattern is read from the corresponding pattern table to calculate the prefetch address, generate a request, and execute the prefetch. Through this scheme, it is possible to adapt to multiple scenarios and accurately identify memory access patterns for more precise data prefetching.

The invention relates to a memory virtualization address substitution efficiency improving method and device, and the method comprises the steps: a core analyzes the received previous address read response data, forms a current address, and sends a memory access request for the current address; after receiving the memory access request of the current address, the off-core Cache control component judges whether the generation of the next address depends on the current address or not; if yes, registering a prefetching start flag and a low address, and judging whether the prefetching request of the current address is executed or not; if the execution is finished, directly generating read response data of the current address; if the execution is not completed, merging the read request of the current address into the prefetch request of the current address, and generating read response data of the current address after receiving data of other cores or main memories; and forming a next address based on the read response data of the current address and the low address, and triggering a pre-fetching request for the next address. According to the invention, the efficiency of replacing the virtual address of the client into the physical address of the host can be improved.

The application provides an instruction processing method, a processor core, a processor, an instruction processing device, a video encoding method, a video decoding method, a video encoding device, a video decoding device, a computer readable storage medium and a computer program product. The instruction processing method comprises the following steps: obtaining a Hadamard transform instruction to be processed; the Hadamard transform instruction is used to indicate a first matrix to be involved in operation; generating a matrix multiplication instruction for the first matrix and generating a matrix transposition instruction for the operation result of the matrix multiplication instruction according to the Hadamard transform instruction; executing the matrix multiplication instruction and the matrix transposition instruction to obtain a target operation result for the Hadamard transform instruction. Therefore, the scheme provided by the application can reduce the number of operator instructions required to be executed in the Hadamard transform, improve the instruction execution efficiency, reduce the data access delay, and improve the end-to-end frame rate in video encoding.