AMBA interface circuit

A technology of interface circuit and main equipment, applied in the direction of electrical digital data processing, instruments, etc., can solve the problems of bus access delay, waste of resources, etc., to reduce waiting time and memory access delay, avoid data packet loss, and save resources Effect

Inactive Publication Date: 2010-05-19
EAST CHINA INST OF OPTOELECTRONICS INTEGRATEDDEVICE
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  • Abstract
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AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is exactly in order to overcome the bus access delay that exists in the interface circuit of existin

Method used

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Example Embodiment

[0027] Such as figure 1 As shown, the AMBA interface circuit of the present invention includes a Master interface circuit, a Slave interface circuit and a bus arbiter. The Master interface circuit is connected to the master device Master, and the Slave interface circuit is connected to the slave device Slave. The bus arbiter is Arbitrate to determine the right to use the bus, and then exchange data between the master device and the slave device.

[0028] Such as figure 2 As shown, the feature of the present invention is that the Master interface circuit has built-in 3 first-in-first-out data buffer FIFOs, among which:

[0029] Write Data FIFO is used to receive the data transmitted from the master device. When the master device has not obtained the right to use the bus, it can write the data into the Write Data FIFO first, and then transmit the data when the right to use the bus is obtained;

[0030] Write Address FIFO is used to receive the address transmitted from the master devi...

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Abstract

The invention relates to an AMBA interface circuit which is characterized in that 3 FIFOs are arranged in a Master interface circuit, wherein the Writer Data FIFO and the Writer Address FIFO are used for receiving the data and the address from the transmission of master equipment; if the master equipment does not obtain the right to use the bus temporarily, the data or the address can be first written into the Writer Data FIFO or the Writer Address FIFO, and the data or the address can be transmitted after the master equipment obtains the right to use the bus; the Read Data FIFO is used for sending data to the master equipment; when the master equipment is busy, the data from the transmission of a Slave equipment can be stored temporarily in the Read Data FIFO, then the bus can be release, and the data can be transmitted when the master equipment can receive the data. Compared with the prior art, the invention has the advantages that firstly, because the FIFOs are arranged in the Master interface circuit, the running of the master equipment and the slave equipment and the transmission of the data or the address can be made concurrent, and the bus waiting time and the access-memory delay can be can be shortened, secondly, because the FIFOs are arranged in the Master interface circuit, the resource can be saved in the process of the transmitting the data or the address by the master equipment and the slave equipment, and thirdly, the loss of the data can be avoided when the Master interface circuit is used for transmitting the network on the chip.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits and relates to an AMBA bus interface circuit. Background technique [0002] Microprocessor core or DSP core, memory, system bus and peripherals have been integrated on one chip. With the development of SoC technology, high-speed data transmission is required to reduce bus access delay and memory access delay. It is necessary to design a bus interface module that can meet high-speed data transmission, so that the operation of the processor core and the data transmission of the peripherals have parallelism, and improve the overall performance of the system. [0003] At present, such as the integrated circuit with the patent No. 02130330.4 and the method of data conversion between the AHB interface of AMBA and the parallel processor in the RISC system of 20071004557.7, most of the interface circuits based on the AMBA bus use registers to transmit data, and it is difficult to...

Claims

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Application Information

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IPC IPC(8): G06F13/40G06F13/42
Inventor 刘艳耿罗峰汪健张多利杜高明
Owner EAST CHINA INST OF OPTOELECTRONICS INTEGRATEDDEVICE
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