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48results about How to "Reduce computing latency" patented technology

Online pipe network anomaly detection system based on machine learning

ActiveCN103580960AImprove exception recognition rateSave human effortData switching networksReal-time dataData mining
The invention discloses an online pipe network anomaly detection system based on machine learning. The online pipe network anomaly detection system comprises a data collection unit, a data distribution unit and a plurality of anomaly detection units. The data collection unit is used for collecting real-time data of an online pipe network, merging the real-time data according to position areas and grouping the real-time data into different data packages. The data distribution unit is used for receiving the data packages, extracting data elements from the data packages and dividing the data packages into a plurality of data subsets after formatting the data packages. The anomaly detection units are used for receiving the data subsets in a one-to-one correspondence mode and predicating anomalism of the data subsets based on a semi-supervised machine learning framework. The anomaly detection units can be used for carrying out parallel data processing, and data transmission can be carried out among the anomaly detection units through an MPI. The online pipe network anomaly detection system can meet the requirements of the online anomaly detection units based on machine learning for usability of a server, and can prevent extra hardware on standby in an idle state from being introduced in.
Owner:FOSHAN LUOSIXUN ENVIRONMENTAL PROTECTION TECH

Large integer multiplication realizing method and device based on vector instructions

ActiveCN104461449AReduce the number of instructionsImprove computing throughputDigital data processing detailsXeon PhiTwo-vector
The invention provides a large integer multiplication realizing method and device based on vector instructions. The multiplicand and the multiplier of the large integer multiplication are each split into one or more vector length integers, the integers are multiplied, and all products are summed; when the integers with two vector lengths are multiplied, product vectors generated by all the vector multiplication instructions form two addition carry chains according to the appointed sequence, the vector addition instructions with carries are utilized for making carries generated by vector addition each time serve as input of the next vector addition instruction, all the addition carries in the chains are eliminated, and only two addition carries are generated and added back to obtain the product of the integers with the two vector lengths. Specifically, if the length of the multiplicand and the length of the multiplier are smaller than 1 / n of the vector length, multiplication of n groups of integers is combined into the one-time multiplication of vector length integers, and the calculation handling capacity is promoted by n times. Based on the large integer multiplication method, the invention further discloses a high-speed large integer multiplication device based on an Intel Xeon Phi co-processor. According to the method, instruction numbers needed by the large integer multiplication method are reduced, calculation delay is reduced, and the calculation handling capacity is improved.
Owner:DATA ASSURANCE & COMM SECURITY CENT CHINESE ACADEMY OF SCI

Power line carrier communication automatic gain control method

The invention discloses a power line carrier communication automatic gain control method, which comprises the following steps: calculating a characteristic function and a decision function; according to relation between the decision function and a detection threshold value and a pulse interference threshold value, calculating gain control amount; and during the process of calculating the gain control amount, according to the relation between the decision function and a preset threshold value and the pulse interference threshold value, stopping calculating the gain control amount and restarting the calculating process. According to the method, the received data can be used directly to carry out gain control judgment; the characteristic function is calculated through an iteration mode; difference between the current signal and the delay signal is calculated every time, and is subjected to add operation with the result obtained in the last calculation, thereby reducing calculation delay and complexity under the condition of ensuring gain calculation precision; and meanwhile, the pulse interference threshold value is set for resisting interference of noise to gain control. Therefore, the method is independent of frame synchronization or symbol synchronization information, can effectively prevent the interference of the noise on the gain control and simplifies gain control value computation complexity.
Owner:WILLFAR INFORMATION TECH CO LTD

Parallel data reflow method under stream computing environment

The invention provides a parallel data reflow method oriented for real-time streaming computation. The method comprises the steps that step 1, initialization of three queues; step 2, initialization of a piping Data Queue; step 3, read requests are initiated by Spout of Topology to the Data Queue; step 4, data in the three queues is read by Data Queue; step 5, whether or not the queue pointed by ToP is empty is determined, if the queue is empty, step 6 is proceeded; if the queue is not empty, step 7 is proceeded; step 6, the data in the From queue is copied to the To queue, and the From queue is cleared; 7, data in the Data Queue is obtained by Topology, a Tuple is sent by current Task to downstream; step 8, the feedback of Tuple awaits for being sent by current Task, if the sending fails or times out and the feedback is not sent, the Tuple is opted to reflow; 9, whether or not the Topology can be stopped is determined, and if the Topology cannot be stopped, then step 4 is proceeded, otherwise, the steps are ended. By the parallel data reflow method oriented for real-time streaming computation, the data is stateless and has fault-tolerance, data computation latency is reduced, system response is increased, and the reflowed data is processed by priority at the first possible chance.
Owner:ZHEJIANG UNIV OF TECH

Data processing method and device and medium

The invention discloses a data processing method and device and a medium, and the method comprises the steps: a first target FPGA acceleration card obtains a calculation start command sent by a target host connected with the first target FPGA acceleration card, carries out the calculation of to-be-processed data, and obtains intermediate result data, the intermediate result data and the next-step calculation type information are sent to the next FPGA accelerator card according to self configuration information, the next FPGA accelerator card calculates the intermediate result data to obtain new intermediate result data, the new intermediate result data and the next-step calculation type information are sent to the next FPGA accelerator card, and the new intermediate result data and the next-step calculation type information are sent to the next FPGA accelerator card. Obtaining final result data until the calculation of the last second target FPGA accelerator card participating in the calculation is completed; and returning the final result data to the target host through the second target FPGA accelerator card so as to complete distributed calculation for the to-be-processed data. According to the invention, the calculation delay of distributed calculation of a plurality of FPGA acceleration cards can be reduced, so that the calculation efficiency is improved.
Owner:LANGCHAO ELECTRONIC INFORMATION IND CO LTD

Streamlined convolution computing architecture design method and residual network acceleration system

The invention provides a streamlined convolution computing architecture design method and a residual network acceleration system. According to the method, a hardware acceleration architecture is divided into an on-chip buffer area, a convolution processing array and a point-by-point addition module; a main path of the hardware acceleration architecture is composed of three convolution processing arrays which are arranged in series, and two assembly line buffer areas are inserted among the three convolution processing arrays and used for achieving interlayer assembly lines of three layers of convolution of the main path. A fourth convolution processing array is set to be used for processing convolution layers, with the kernel size being 1 * 1, of the branches of the residual building blocks in parallel, a register in the fourth convolution processing array is configured, the working mode of the fourth convolution processing array is changed, the fourth convolution processing array can be used for calculating a residual network head convolution layer or a full connection layer, and when the branches of the residual building blocks are not convolved, the fourth convolution processing array is skipped out and convolution is not exected; and a point-by-point addition module is set to add corresponding output feature pixels element by element for the output feature of the main path of the residual building block and the output feature of the branch quick connection.
Owner:SUN YAT SEN UNIV

Small-scale pedestrian target rapid super-resolution method for intelligent roadside equipment

ActiveCN112132746AReduce the number of training iterationsQuality improvementImage enhancementImage analysisImage resolutionSimulation
The invention discloses a small-scale pedestrian target rapid super-resolution method for intelligent roadside equipment. The method comprises the steps of collecting and constructing a small-scale pedestrian high-low resolution data training set; based on a generative adversarial idea, building a lightweight generative network for a low-resolution small-scale pedestrian image. The network firstlyuses separable convolution to extract image preliminary features, then combines a residual module to fit high-frequency information, and finally uses a pixel recombination module to perform high-resolution reconstruction on the low-resolution pedestrian image. A discrimination network is built, and discrimination training is performed on the parameters of the generation network to obtain an optimal generation network; and super-resolution on the low-resolution small-scale pedestrian picture is performed by using the optimal generation network to obtain a high-resolution pedestrian target. Thelightweight super-resolution generation network designed by the invention has the remarkable advantages of short training time and low reasoning delay, and fills the technical gap of small-scale pedestrian real-time super-resolution in the field of intelligent roadsides.
Owner:SOUTHEAST UNIV

An online pipe network anomaly detection system based on machine learning

ActiveCN103580960BImprove exception recognition rateSave human effortData switching networksReal-time dataNetwork packet
The invention discloses an online pipe network anomaly detection system based on machine learning. The online pipe network anomaly detection system comprises a data collection unit, a data distribution unit and a plurality of anomaly detection units. The data collection unit is used for collecting real-time data of an online pipe network, merging the real-time data according to position areas and grouping the real-time data into different data packages. The data distribution unit is used for receiving the data packages, extracting data elements from the data packages and dividing the data packages into a plurality of data subsets after formatting the data packages. The anomaly detection units are used for receiving the data subsets in a one-to-one correspondence mode and predicating anomalism of the data subsets based on a semi-supervised machine learning framework. The anomaly detection units can be used for carrying out parallel data processing, and data transmission can be carried out among the anomaly detection units through an MPI. The online pipe network anomaly detection system can meet the requirements of the online anomaly detection units based on machine learning for usability of a server, and can prevent extra hardware on standby in an idle state from being introduced in.
Owner:FOSHAN LUOSIXUN ENVIRONMENTAL PROTECTION TECH

A crop disease and insect pest identification system and identification method based on edge computing

The invention discloses an edge computing-based crop disease and insect pest identification system and its identification method, comprising: an image conversion module, a signal anti-interference module, a signal adjustment module, an A / D conversion module, a control module, a storage module, a wireless transmission module, The wireless receiving module, the image conversion module converts the received image acquisition signal into an electrical signal; the signal anti-interference module filters the interference signal generated in the conversion; the signal adjustment module performs the signal detection by the image acquisition component. adjustment; the A / D conversion module converts the analog signal into a digital signal; the control module obtains the detection signal, so that the next-level module operates; the storage module stores the collected image information; the wireless transmission module will The received image signal is converted into a wireless signal, thereby realizing remote monitoring; the wireless receiving module receives the transmission of the digital image, thereby realizing the fast transmission of the detection signal and reducing the calculation delay.
Owner:NANJING COREWELL CLOUD COMPUTING INFORMATION TECH CO LTD
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