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Fixed point vector processor and vector data access controlling method thereof

A vector processor and data control technology, applied in the direction of machine execution devices, etc., can solve the problems of low versatility, low computing performance, high power consumption and delay, etc., to achieve enhanced reusability, improved computing performance, and flexible configuration. Effect

Inactive Publication Date: 2015-06-10
HARBIN INST OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The present invention proposes in order to solve the following problems: 1) general-purpose processor software for kernel method realizes the problems of low computing performance, power consumption and large delay; 2) existing vector processors cannot be optimized for specific methods. The problem of poor versatility and inability to meet the needs of online computing; 3) The existing vector processors cannot take into account the computing performance and FPGA on-chip computing resource consumption

Method used

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  • Fixed point vector processor and vector data access controlling method thereof
  • Fixed point vector processor and vector data access controlling method thereof
  • Fixed point vector processor and vector data access controlling method thereof

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specific Embodiment approach 1

[0028] Specific implementation mode 1, refer to figure 1 Specifically illustrate the present embodiment, the fixed-point vector processor described in the present embodiment, it comprises program counter 1, microcode memory 2, vector memory 3, arithmetic logic unit 4 and data control unit 5;

[0029] The program counter 1 is used to receive the counting instruction sent by the data control unit 5 and the input target address microcode instruction sent by the microcode memory 2, and output the count value to the microcode memory 2;

[0030] The microcode memory 2 is used to receive and store the count value sent by the program counter 1, and output the path index L microcode instruction to the data control unit 5, and simultaneously output the OP microcode instruction to the arithmetic logic unit 4 and the data control unit 5, and output the input Vector address microcode instructions to vector memory 3, output and input target address microcode instructions to program counter ...

specific Embodiment approach 2

[0037] Embodiment 2. This embodiment is a further description of the fixed-point vector processor described in Embodiment 1. In this embodiment, the vector memory 3 includes a vector memory 1, a vector memory 2, ..., a vector memory N; ALU 4 includes ALU 1, ALU 2, ..., ALU N; wherein, N is an integer greater than or equal to 1 and less than or equal to 128; vector memory 1 is connected to ALU 1 and forms a data path , and the vector memory 1 and the ALU 1 have the same data bit width; the vector memory 2 is connected to the ALU 2 to form a data path, and the vector memory 2 and the ALU 2 have the same data bit width; ... ; The vector memory N is connected to the arithmetic logic unit N to form a data path, and the vector memory N and the arithmetic logic unit N have the same data bit width.

[0038] Each vector memory forms a data path with the ALU, the two are directly connected, and have the same data bit width M.

specific Embodiment approach 3

[0039] Specific Embodiment 3. This embodiment is a further description of the fixed-point vector processor described in Embodiment 1. In this embodiment, the number of data paths formed by the vector memory 3 and the ALU 4 is 1-128.

[0040] In the prior art, the number of lanes of a vector processor is currently limited to powers of 2 (16, 32, 64, 128). In this embodiment, the number of data paths of the vector processor 3 can be flexibly set according to specific calculation needs. In order to reduce the complexity of hardware design, according to the design method in this paper, vector processing with any number of data paths from 1 to 128 can be realized. device. The vector processor design is a highly portable vector processor design, which can be easily transplanted to other FPGA devices.

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Abstract

The invention discloses a fixed point vector processor and a vector data access controlling method thereof, relates to a vector processor used for online time series prediction and aims to solve the problems that an existing vector processor incapable of optimizing a specific method is poor in universality and cannot satisfy requirements on online computation. The fixed point vector processor comprises a program counter, a microcode memorizer, a vector memorizer, an arithmetic logic unit and a data control unit. A complete fixed point vector processing procedure is formed by every signal processing procedure of the program counter, the microcode memorizer, the vector memorizer, the arithmetic logic unit and the data control unit. By means of ALU (arithmetic logic unit) designing, an ALU structure of each data path can be changed flexibly according to computation needs, flexible configuration of an instruction set is achieved, and accordingly, the fixed point vector processor and the vector data access controlling method are applicable to occasions required by complex computation.

Description

technical field [0001] The invention relates to a fixed-point vector processor with high performance, low power consumption and low delay, in particular to a vector processor for online time series prediction. Background technique [0002] At present, online machine learning for embedded high-performance computing platforms has become a research hotspot. The high-performance, low-power and low-latency cyber-physical system nodes with online data processing functions integrate information collection, intelligent information processing, and network communication. The functions are highly integrated and are widely used in the fields of environment, industrial production and aerospace engineering. However, for online applications, nonlinear methods need to continuously add new samples and update the model. The ever-increasing sample size and the large amount of calculation required for model updating pose a great challenge to the performance of embedded computing platforms. The...

Claims

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Application Information

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IPC IPC(8): G06F9/30
Inventor 庞业勇王少军何永福刘大同彭宇彭喜元
Owner HARBIN INST OF TECH
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