The invention relates to the technical field of
wafer-level test
anomaly detection, and discloses a
chip wafer-level test
anomaly detection method based on multi-dimensional parameter
correlation analysis, which comprises the following steps: acquiring and preprocessing
wafer test core parameters and equipment operation parameters, constructing a dynamic parameter correlation
reference model, and establishing a dynamic parameter correlation
reference model; the fusion correlation deviation degree of real-time parameters and a normal
correlation coefficient matrix is calculated, a scene exclusive dynamic threshold value is set, explicit and implicit anomaly judgment is completed in combination with a
single parameter specification, and anomaly
source tracing is achieved through a dynamic correlation
list,
feature screening and
time sequence-space two-dimensional detection. The
hybrid algorithm is adopted to calculate the correlation deviation degree, linear and
nonlinear methods are fused to screen features, the defect that only dominant anomalies can be recognized in the prior art is broken through, collaborative accurate detection of hidden anomalies and dominant anomalies in specifications is achieved, meanwhile, the anomaly root can be traced, dynamic changes of the wafer manufacturing process are adapted, and the detection accuracy is improved. And the comprehensiveness and accuracy of
anomaly detection are improved.