Vector processor and vector data access and interaction method thereof

Abstract

The invention discloses a vector processor and a vector data access and interaction method thereof. The vector processor comprises an address register set, an address generation logic unit and a data interaction logic unit, wherein the address register set is used for storing an operand and vectorized address data and transmitting the vectorized address data to a memory set through an address bus interface, and the vectorized address data are used for accessing the memory set; the address generation logic unit is used for calculating the vectorized address data according to the operand through an arithmetic logic unit and storing the vectorized address data in the address register set; the data interaction logic unit is used for carrying out splitting / splicing operation on vector data, which are accessed from the memory set through the address bus interface, through the arithmetic logic unit. According to the vector processor and the vector data access and interaction method thereof, the efficient arithmetic logic unit of the vector processor can be utilized sufficiently, so that the data processing speed is high and the efficiency is high.

Description

technical field

[0001] The invention relates to data processing, in particular to a vector processor and a method for vector data access and interaction. Background technique

[0002] figure 1 It is a schematic diagram of the existing vector processor data access structure, as shown in the figure, in the existing vector processor data storage mechanism, the components involved mainly include: the vector processor 101, the access address line 102 of the vector processor , a data line 103, a data bus 104, an address generation control logic unit 105, a data disassembly logic unit 106, and a memory bank 107 composed of n memories.

[0003] When vector data access occurs, the vector processor 101 sends an initial address through the access address line 102, and this initial address is used as the input of the address generation control logic unit 105, and a group of address signals are obtained through the calculation of the address generation control logic unit 105, so The ab...

Images