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Matrix preprocessing method and device, terminal and readable storage medium

A preprocessing, matrix technology, applied in memory systems, machine execution devices, electrical and digital data processing, etc., can solve problems such as low scalability, flexibility, and specificity

Pending Publication Date: 2019-10-29
GUANGDONG COMM & NETWORKS INST
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The main purpose of the present invention is to provide a matrix preprocessing method, which aims to solve the technical problems of existing matrix operation accelerators, strong specialization, low scalability and flexibility

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  • Matrix preprocessing method and device, terminal and readable storage medium
  • Matrix preprocessing method and device, terminal and readable storage medium
  • Matrix preprocessing method and device, terminal and readable storage medium

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Embodiment Construction

[0017] It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0018] Such as figure 1 as shown, figure 1 It is a schematic structural diagram of a terminal in the hardware operating environment involved in the solution of the embodiment of the present invention.

[0019] Such as figure 1 As shown, the terminal may include: a processor 1001 , such as a CPU, a network interface 1004 , a user interface 1003 , a memory 1005 , and a communication bus 1002 . Wherein, the communication bus 1002 is used to realize connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit such as a keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface and a wireless interface. Optionally, the network interface 1004 may include a standard wired interface and a wireless interface (...

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Abstract

The invention discloses a matrix preprocessing method. The method comprises the following steps: when receiving a matrix preprocessing instruction, acquiring parameters of a first matrix, parameters of a second matrix and parameters of a DMA segmentation matrix based on the preprocessing instruction, generating the first block matrix and the second block matrix based on the parameters of the firstmatrix and the parameters of the DMA segmentation matrix, and storing the first block matrix and the second block matrix in the preset DMA operation cache region. The invention further discloses a device, a terminal and a readable storage medium. An existing matrix operation unit can be flexibly used as a matrix basic operation resource, operation functions such as multiplication, addition or transposition of a large matrix can be efficiently, conveniently and rapidly achieved, and the problems of flexibility, universality, expandability and reusability of matrix operation processing are solved while the processing performance and the operation efficiency of matrix operation are guaranteed.

Description

technical field [0001] The present invention relates to the technical field of digital signal processing, in particular to a matrix preprocessing method, device, terminal and readable storage medium. Background technique [0002] Matrix operations are widely used in many fields such as digital signal processing, deep learning, image recognition, artificial intelligence, and channel coding. Due to high computational complexity and low processing efficiency, they often become the bottleneck of system computing performance, especially for large-scale matrix operations. They all appear in many digital signal processing systems in the form of a coprocessor or accelerator in the form of DMA. The implementation of this matrix operation is highly specific, and matrix addition, matrix multiplication, and matrix transposition are different. The implementation schemes of matrix processing are very different. Even if it is the same design scheme, when the functions or performance indica...

Claims

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Application Information

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IPC IPC(8): G06F17/16G06F9/30G06F9/38G06F12/02
CPCG06F17/16G06F9/30036G06F9/3867G06F12/0238Y02D10/00
Inventor 曹建业
Owner GUANGDONG COMM & NETWORKS INST
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