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LDPC (Low Density Parity Check) encoding method based on FPGA (Field Programmable Gate Array) and used in CMMB (China Mobile Multimedia Broadcasting) exciter

A coding method and technology of an exciter, which are applied in error detection coding using multi-bit parity bits, error correction/detection using block codes, data representation error detection/correction, etc. Linear complexity, unrealistic implementation and other problems, to achieve the effect of simplifying logical operation operations, reducing coding complexity, and saving storage space

Inactive Publication Date: 2012-10-17
ALLWIN TELECOMM
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Problems solved by technology

Therefore, one of the main problems faced by LDPC codes is its high coding complexity and coding delay.
[0046] In the CMMB system, each row of the G matrix obtained by the above method has more than 1000 elements equal to 1, which will result in too much storage required and too high encoding complexity, making it unrealistic to implement
[0047] (2) Two matrix-vector multiplications in the general coding method of linear block codes. In the first multiplication, B is a sparse matrix. The multiplication of a sparse matrix and a vector is linear complexity, but in the second multiplication A -1 It is no longer a sparse matrix, so it is no longer linear complexity when multiplying vectors
The disadvantage of this algorithm is that the general H matrix does not have an approximate lower triangular structure, and the H matrix must be rearranged first, but when rearranging, it is difficult to ensure the form of the H matrix system code, and the transformed The submatrix T of the H matrix is ​​reversible, so it has certain limitations
[0049] To sum up, the main problems faced by the LDPC coding of the CMMB standard are its large parity check matrix, high coding complexity and long coding delay.

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  • LDPC (Low Density Parity Check) encoding method based on FPGA (Field Programmable Gate Array) and used in CMMB (China Mobile Multimedia Broadcasting) exciter
  • LDPC (Low Density Parity Check) encoding method based on FPGA (Field Programmable Gate Array) and used in CMMB (China Mobile Multimedia Broadcasting) exciter
  • LDPC (Low Density Parity Check) encoding method based on FPGA (Field Programmable Gate Array) and used in CMMB (China Mobile Multimedia Broadcasting) exciter

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Embodiment Construction

[0078] The specific embodiment of the present invention will be further described below in conjunction with accompanying drawing:

[0079] In the CMMB exciter, for different channels and transmission content, the LDPC code has two different code rates of 1 / 2 and 3 / 4 to choose from. If the code rate is selected, the information bit length for each LDPC encoding is fixed. The fixed length forming each codeword is 9216 bits. LDPC output code word C={c 0 , c 1 ,... c 9215} by the input information bit S={s 0 ,s 1 ,...s k-1} and parity bits P={p 0 ,p 1 ,…p 9215-K}, rearrange according to the following formula:

[0080] The description of the LDPC encoding module in the CMMB standard: the input information bit sequence vector S and the check bit sequence vector P are rearranged to obtain the LDPC output codeword.

[0081] C COL _ ORDER ( i ...

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Abstract

The invention discloses an LDPC (Low Density Parity Check) encoding method based on FPGA (Field Programmable Gate Array) and used in CMMB (China Mobile Multimedia Broadcasting) exciter. The method comprises the following steps: firstly, processing a verification matrix H of an LDPC system code on an MATLAB (Matrix Laboratory) platform, so as to generate verification matrixes Hp and Hs which correspond to a verification bit column vector P and an information bit column vector S; carrying out LU (Logical Unit) decomposition to the verification matrixes so as to obtain a lower triangular matrix L and an upper triangular matrix U; and realizing the LDPC encoding on the FPGA platform, which mainly involves the storage of a large matrix, matrix multiplication, forward iteration and backward iteration. According to the encoding method, an encoding mode based on a LU decomposition verification matrix is adopted; the logic calculation that large matrixes are multiplied is avoided; and the problem of large requirement on FPGA internal storage resource caused by large data quantity storage is solved, thereby simplifying the logic calculation operation, saving the storage space, and being beneficial for the realization of the LDPC encoding of the CMMB system.

Description

technical field [0001] The invention is aimed at the LDPC coding in the CMMB standard, and the coding method used is also applicable to the LDPC coding based on a large sparse parity check matrix. Background technique [0002] LDPC (Low Density Parity Check Codes, Low Density Parity Check Codes) has attracted much attention for its excellent error correction performance and low decoding complexity, and has been widely used in communication and digital broadcasting and other fields. One of the main problems faced by LDPC coding is its high coding complexity and coding delay. How to choose a suitable algorithm to achieve a balance between resources and efficiency is the main difficulty in hardware implementation of LDPC encoding. [0003] Description of the LDPC encoding module in the CMMB standard: [0004] The input information bit string vector S and check bit string vector P are rearranged to obtain the LDPC output codeword. [0005] C ...

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Application Information

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IPC IPC(8): H03M13/11
Inventor 郝禄国杨建坡洪维娜方壮潮余嘉池杨舜君何仕杰曾文彬
Owner ALLWIN TELECOMM
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