11 results about "Matrix manipulation" patented technology

The invention discloses an employee ability assessment method and system based on a structure attribution neural network, and a medium, and belongs to the field of power systems, and the method comprises the steps: extracting the partial derivative information of an ability assessment model based on a gradient back propagation mechanism, determining the gradient sensitivity based on each partial derivative information, and determining a weight parameter; processing the real-time evaluation event according to the weight parameter to obtain a target evaluation event, and performing matrix processing and division according to the index service dimension to obtain a plurality of sub-matrixes, so that the capability evaluation model splices feature extraction results output after extraction of the plurality of structure sub-networks for each sub-matrix into an intermediate vector, the intermediate vector is predicted through the summary regression network, a target evaluation result is output, the structure dimension of each structure sub-network is in one-to-one correspondence with the service dimension, and the model adopts a loss function based on attribution guidance, so that objective and accurate evaluation of the ability of the to-be-evaluated employee can be realized through implementation of the method and the system.

This application provides a data processing method and a readable storage medium based on a matrix processor. The method includes: reading W first elements from a first matrix and sending the W first elements to a computing unit of the matrix processor for calculation; wherein W is greater than the width N of the first matrix and less than or equal to the number K of the computing units of the matrix processor; repeating the above steps until the number of remaining elements in the first matrix is ​​less than W; and in response to the number of remaining elements in the first matrix being non-zero, sending the remaining elements to the computing unit for calculation. This method can improve the utilization rate of the matrix processor's computing units, reduce the number of calculation cycles, shorten the calculation time, and fully utilize the computing units of the matrix processor.

The invention discloses a weight matrix processing method and device, equipment, a storage medium and a product. The method comprises the steps that a target weight matrix is loaded; wherein the target weight matrix is a third-precision weight matrix which is arranged in a preset format and is formed by packaging a first-precision weight matrix; carrying out unpacking and inverse quantization processing on the target weight matrix to obtain a weight matrix with second precision; wherein the third precision is higher than the second precision, and the second precision is higher than the first precision; and storing the weight matrix with the second precision to an on-chip storage unit so as to be loaded to a tensor core to execute matrix multiplication operation. According to the embodiment of the invention, the weight matrix can be compatible with the operation logic of tcore, so that the matrix multiplication operation can be smoothly completed in the tcore.

For purposes of compression and decompression operations, a tensor is split into tiles having a tile size, and values at a given position in the respective tiles are processed as a stream. In some example implementations, for compression operations, a matrix processing tool can separately apply variable-rate compression to different streams of values of the tensor, with the different streams being associated with different positions of the tile size. For decompression operations, the matrix processing tool can quickly reconstruct different streams of values of the tensor. The decompression operations can be performed in parallel, with different decoders decompressing different streams of values of the tensor. In this way, soon after decompression starts, tensor blocks of values of the tensor can be loaded to local memory of tensor cores for matrix multiplication and accumulation operations, which can help reduce latency and fully utilize the tensor cores.

The application discloses a hardware architecture and a design space exploration method for accelerating multi-channel convolution, comprising an external storage module, a preprocessing module, a cache module, a matrix multiplication module and an output dimension rearrangement module, the external storage module is connected to the preprocessing module, the preprocessing module is connected to the cache module, the cache module is connected to the matrix multiplication module, the matrix processing module is connected to the output dimension rearrangement module; a task level pipeline is formed among the preprocessing module, the cache module and the matrix multiplication module, and parallel processing of three tasks of matrixing of a feature map and a convolution kernel, intermediate value caching and matrix multiplication operation is realized. The application converts multi-channel convolution into matrix multiplication and accelerates the same through design of a hardware structure, simultaneously proposes a design space exploration method based on performance and execution time, maximally improves resource utilization, and efficiently realizes real-time calculation of multi-channel convolution.

The application discloses a weight matrix processing method and device based on ReRAM, and the method comprises the following steps: acquiring the activated row number and the activated column number of a memistor ReRAM; performing non-structure pruning and compression on a weight matrix to obtain a compressed matrix block, wherein the row number of the compressed matrix block is less than or equal to the activated row number, the column number of the compressed matrix block is less than or equal to the activated column number, the row positions of each weight value in the same row in the compressed matrix block correspond to the same row position of the weight matrix, and the column positions of each weight value in the same column in the compressed matrix block correspond to the same column position of the weight matrix. By implementing the application, the matching application of the compressed matrix block and the ReRAM can be realized, the utilization efficiency of the ReRAM is improved, and the operation of the neural network is accelerated.

For purposes of compression and decompression operations, a tensor is split into tiles having a tile size, and values at a given position in the respective tiles are processed as a stream. In some example implementations, for compression operations, a matrix processing tool can separately apply variable-rate compression to different streams of values of the tensor, with the different streams being associated with different positions of the tile size. For decompression operations, the matrix processing tool can quickly reconstruct different streams of values of the tensor. The decompression operations can be performed in parallel, with different decoders decompressing different streams of values of the tensor. In this way, soon after decompression starts, tensor blocks of values of the tensor can be loaded to local memory of tensor cores for matrix multiplication and accumulation operations, which can help reduce latency and fully utilize the tensor cores.

The present disclosure provides a data format conversion method and device, and a matrix processing method and device, and relates to the technical field of computers, in particular to the technical field of artificial intelligence, deep learning, chips and the like. The specific implementation scheme of the data format conversion method is as follows: determining a maximum value of a target matrix according to each element in the target matrix; determining an offset according to a numerical value distribution interval of each element; determining a plurality of continuous numerical value intervals according to a numerical digit width of an index bit of a target data format, the offset and the maximum value of the target matrix; and converting an original data format of the target matrix into the target data format according to a corresponding relationship between each element and the plurality of numerical value intervals and a corresponding relationship between the plurality of numerical value intervals and the target data format. According to the scheme of the present disclosure, the operation amount of data format conversion can be reduced, and the quantization precision of each element in the target matrix can be improved while considering the numerical value range that can be represented by each element.

and an operand storage circuit configured to store information for forming the first and second input operands for the matrix processing circuit, and a masking circuit configured to perform a masking operation to mask at least a portion of the matrix processing operation or information stored in the operand storage circuit based on masking state data indicating the locations of one or more masked rows or columns that are processed to represent masked values. This is useful for improving performance of 2D convolution operations because masking can be used to mask selected rows or columns when performing 2D convolution as a series of 1×1 convolution operations applied to different kernel positions.

An N-channel alternating analog-to-digital converter (ADC) with variable delays added to the input sampling clock of each ADC. During calibration, these variable delays are programmed by a successive approximation register (SAR) to minimize time phase mismatch between channels. Within each channel, the ADC output is filtered, and a product derivative correlator generates a product derivative factor of the correlation between two adjacent ADC channels. A matrix processor arranges the product derivative factors from the product derivative correlator into a matrix and multiplies this matrix by a correlation matrix. The correlation matrix is ​​a constant generated by an N×N shift matrix. The matrix processor outputs a sign bit vector. Each bit in the sign bit vector determines when to set or clear a test SAR bit to adjust the variable delay of the channel. Sampling clock and time phase mismatch can be reduced to one LSB across all N channels.

The application discloses a matrix compression method, a matrix processing method and related devices, and belongs to the field of data processing. The method comprises the following steps: dividing a first matrix stored in a memory to obtain a plurality of first sub-matrices; compressing non-zero element groups in each first sub-matrix in the plurality of first sub-matrices according to a first direction to obtain a plurality of second sub-matrices corresponding to the first matrix; dividing each second sub-matrix in the plurality of second sub-matrices to obtain a plurality of third sub-matrices; and generating a compression result of the first matrix based on the plurality of third sub-matrices. According to the application, only non-zero element groups exist in the first sub-matrices, so that a part of elements with a value of zero in the first matrix is removed, and therefore, the compression result of the first matrix can effectively reduce the number of zero elements that need to be stored, thereby saving data storage space.