49results about How to "Utilization area" patented technology

The invention provides a charging device that uses switched capacitor voltage converters to charge a battery using solar power. The charger uses boosting topology to efficiently use solar module photovoltaic power. The boosting topology enables a lower voltage to be used resulting in reduced cutting and soldering of photovoltaic cells. The battery charger has overcharge protection and uses inductor-less circuitry.

A low power consumption display device and an electronic appliances are provided. The display device of the invention comprises a pixel region including a plurality of pixels, a source driver, a first gate driver, and a second gate driver. Each of the plurality of pixels includes a light emitting element, a first transistor for controlling a video signal input to the pixel, a second transistor for controlling emission/non-emission of the light emitting element.

Even when an assignment request of storage areas exceeding unassigned areas is issued from a server, storage areas can be assigned to the server, so that storage areas in a storage pool can be utilized effectively. A management server connected to a plurality of servers and storage apparatuses to manage physical storage areas of the storage apparatuses used by the plurality of servers as virtual areas (storage pool) is responsive to an area assignment instruction of storage areas exceeding unassigned areas received from a server to release at least part of assignment areas of other servers to be assigned to the server which issued the area assignment instruction.

In accordance with a parallel matrix processing method adopted in a shared-memory scalar computer, a matrix to be subjected to LU factorization is divided into a block D of the diagonal portion and blocks beneath the D diagonal block such as L1, L2 and L3. Then, D+L1, D+L2 and D+L3 are assigned to 3 processors respectively for processing them in parallel. Next, a block U is updated by adopting an LU-factorization method and C1 to C3 are updated with L1 to L3 and U. By carrying out this processing on the inner side gradually decreasing in size as blocks, finally, a portion corresponding to the D diagonal block remains to be processed. By applying the LU factorization to this D portion, the LU factorization for the entire matrix can be completed.

A snow pusher, also known as a box plow has a blade that is configured to be disposed in a first position for pushing snow forwardly, as is typical of snow pushers, and is further configured to be disposed in a second position for pulling snow rearwardly. The blade of the snow pusher may be contained within a snow plow box that may be reversible, allowing the blade to be disposed at a rear of the box for pushing the snow forwardly and at a front of the box for pulling snow rearwardly.

A storage area management method for a data storage apparatus partitions an acquired storage area into storage areas with differing power-of-2 sizes and manages each of them. Also, a storage area allocation method receives an allocation request for a storage area that includes a requested allocation size, and acquires an available storage area whose size is the smallest power-of-2 size encompassing the requested allocation size, and obtains a binary expression of the requested allocation size, and in response to the received allocation request, allocates a contiguous storage area comprised of storage areas each of whose size is a power of 2 of a value of a bit position wherein a 1 is set in the binary expression.

An averaged impedance calibration is obtained by utilizing two separately controlled resistive loads arranged in parallel and choosing two adjacent control codes to configure switch arrays to set the resistance of each of the separate resistive loads. The resistance of the resistive loads is averaged to provide greater accuracy. The two adjacent control codes are close to the target impedance value and typically one is slightly higher and one is slightly lower than the target impedance value.

A method for optimizing area array device pin utilization and reducing the number of layers on a multilayered PCB comprising: preparing a package of BGA pin-out maps which anticipate the effect of existing fixed pins and derives the resulting optimum pin location assignment. Each pin-out map includes an indication of the best routing for circuits from a given component to be mounted to a PCB. Applying the package of pin-out maps during an area array pin assignment phase, thereby making an area array package capable of supporting the optimum routing configuration proposed by the pin-out maps. Applying the package of pin-out maps during a PCB design phase so that the optimum circuit routing to each pin is achieved, thereby completing the strategy layed out by the proposed pin-out maps, resulting in a lower number of PCB layers.

The present invention relates to the field of semiconductor switches, and relates more particularly to a GaN-based bidirectional switch device. The present invention provides a gate-controlled tunneling bidirectional switch device without Ohmic-contact, which avoids a series of negative effects (such as current collapse, incompatibility with traditional CMOS process) caused by the high temperature ohm annealing process. Each insulated gate structure near schottky-contact controls the band structure of the schottky-contact to change the working state of the device, realizing the bidirectional switch's ability of bidirectional conducting and blocking. Due to the only presence of schottky in this invention, no heavy elements such as gold is needed, and this device is compatible with traditional CMOS technology.

An electronic device including a substrate and an optoelectronic device package is provided. The optoelectronic device package includes a light source, an image sensor and a plurality of connecting pins. The light source is configured to emit light toward a direction of a bottom surface of the optoelectronic device package. The image sensor is configured to receive reflected light from the direction of the bottom surface. The connecting pins are bended toward an opposite direction of the direction of the bottom surface and electrically connected to the substrate thereby increasing a discharge path of the electrostatic discharge.

It is provided a memory management method for releasing an unnecessary area in a memory area used by a program stored in the memory and executed by the computing device. The memory management method including the step of: setting in the memory, a first memory area which is used to execute the program; setting in the memory, a second memory area which can be operated by the program; setting a utilized area in the second memory area based on an instruction from the program; storing objects including data in the utilized area of the second memory area based on an instruction from the program; determining whether the program uses the objects stored in the utilized area within the second memory area; and releasing, by the computing device, the utilized area occupied by an object that is not used by the program among the objects stored in the utilized area.

A method of manufacturing three-dimensional semiconductor device, comprising the steps of: a) forming a device unit on a substrate, the said device includes a plurality of stack structures composed of the first material layer and the second material layer stacked along a direction perpendicular to the substrate surface; b) forming a contact lead-out region around the said device unit, the contact lead-out region comprises a plurality of sub-partitions, each of the sub-partitions respectively exposes a different second material layer; c) forming a photoresist on said substrate, covering said plurality of sub-partitions, exposing a portion of said second material layer; d) using the photoresist as a mask, simultaneously etching the portion of the second material layer exposed by said plurality of sub-partitions, until another second material layer beneath said second material layer is exposed; e) slimming the size of the photoresist to expose a portion of said another second material layer; f) repeating said steps d and step e, until all of the second material layers are exposed; g) forming contact leads, connecting each of the plurality of the second material layers. In accordance with the method of the present invention, the total number of etching process steps is reduced dramatically and the area utilization is improved effectively by selectively etching each of the sub-partitions.

Disclosed herein are methods for determining the amount or activity of one or more luciferases and methods for measuring the luminescent signal generated by one or more luciferases in a sample, the methods comprising incubating the sample with a reactive substrate(s) of the luciferase(s) to be analysed and a reducing agent to inactivate a first luciferase, wherein the first luciferase, in its native form, is a secreted luciferase.

A semiconductor integrated circuit includes a first circuit, a second circuit, a memory circuit having a plurality of flip-flops, a storage unit, a signal generating unit to produce an operation mode setting signal, a control circuit configured to cause the memory circuit to operate such that the plurality of flip-flops holds a value for setting characteristics of the first circuit when the operation mode setting signal indicates a first operation mode, and configured to cause the memory circuit to operate as a counter to measure a time length used in the second circuit when the operation mode setting signal indicates a second operation mode, and a setting circuit configured to cause trimming data stored in the storage unit to set the characteristic of the first circuit when the operation mode setting signal indicates the second operation mode, the trimming data corresponding to the value held by the memory circuit.

The present invention provides an on-screen display device that can effectively utilize a part of a video RAM area for characters which perform special character display. This on-screen display device includes a register that retains information for performing special character display of respective lines, such as through display or space display, and compares display information of the respective line between the register and a display line counter, to output information indicating whether the special character display is to be performed or not to the video RAM, thereby effectively utilizing a part for performing the special character display in the video RAM area.

A high-voltage field-effect device contains an extended drain or “drift” region having a plurality of JFET regions separated by portions of the drift region. Each of the JFET regions is filled with material of an opposite conductivity type to that of the drift region, and at least two sides of each JFET region is lined with an oxide layer. In one group of embodiments the JFET regions extend from the surface of an epitaxial layer to an interface between the epitaxial layer and an underlying substrate, and the walls of each JFET region are lined with an oxide layer. When the device is blocking a voltage in the off condition, the semiconductor material inside the JFET regions and in the drift region that separates the JFET regions is depleted. This improves the voltage-blocking ability of the device while conserving chip area. The oxide layer prevents dopant from the JFET regions from diffusing into the drift region and allowing the JFET regions to be accurately located in the drift region.

A communication apparatus includes a sharing unit configured to share a communication parameter for wireless communication with another communication apparatus with the another communication apparatus, a connection unit configured to connect to the another communication apparatus using the communication parameter shared by the sharing unit, a communication unit configured to, after connection with the another apparatus by the connection unit, communicate with the another communication apparatus by utilizing a predetermined function, and a control unit configured to control the communication parameter shared by the sharing unit according to a result of communication by the communication unit utilizing the predetermined function.