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SOC verification system and method based on UVM

A verification system and system-on-chip technology, applied in the field of UVM-based SOC verification system, to achieve the effect of ensuring correctness, avoiding repeated development, and ensuring test flexibility

Active Publication Date: 2021-08-24
杭州德旺信息技术有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Verification occupies 80% of the time in the entire chip design work. How to quickly and accurately build a verification platform, develop effective verification incentives, and find out design problems as soon as possible brings huge challenges to the verification work.

Method used

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  • SOC verification system and method based on UVM
  • SOC verification system and method based on UVM
  • SOC verification system and method based on UVM

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0025] The verification object in this embodiment is a high-performance and low-power general-purpose system-on-chip SOC with risc-v as the core. There are buses AXI (Advanced Extensible Interface), AHB (Advanced Highperformance Bus), and APB (Advanced Peripheral Bus) in the system-on-chip SOC. The bus AXI is an on-chip bus for high performance, high bandwidth, and low latency. The bus AHB is mainly used for connection between high-performance modules (such as CPU, DMA and DSP, etc.). The bus APB is mainly used for the connection between low-bandwidth peripherals, such as UART, 1284, etc.

[0026] Specifically, different IPs are connected to corresponding buses according to bus characteristics and IP performance requirements. DDR and DMA modules are hung on the AXI bus, USB and Ethernet IPs are hung on the AHB bus, and IIC / UART / SPI and other IPs are hung on the APB bus.

[0027] This embodiment proposes a UVM-based SOC verification system, including randomly generated test ...

Embodiment 2

[0039]Based on the UVM-based SOC verification system proposed in Embodiment 1, correspondingly, in terms of methods, this Embodiment 2 proposes a UVM-based SOC verification method, such as image 3 As shown, it specifically includes the following steps:

[0040] S1: When verifying the data sent by the peripheral equipment to the SOC of the system on chip, the verification environment is directly multiplexed to generate and send the stimulus signal, and the scoreboard accesses the core register through the back door, and automatically compares with the expected value of the reference model to obtain the verification result;

[0041] S2: When verifying the data sent by the SOC to the bus, the stimulus generator and driver are turned off, the driver is loaded into the risc-v kernel, the on-chip bus drives the IP module to send data, the monitoring module collects and sends data, and the scoreboard performs Judgment of the final result.

[0042] The technical solutions and techni...

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Abstract

The invention relates to the technical field of chip verification, in particular to an SOC verification system and method based on UVM, and the system comprises a test excitation which covers design specifications and is randomly generated, a verification environment layer which is formed by combining a plurality of IP_ENVs, and a system-on-chip SOC based on a risc-v kernel. Each IP_ENV comprises a scoreboard, a kernel register, a reference model, an excitation generator, a driver and a monitoring module. When data sent by peripheral equipment to the SOC is verified, a verification environment is directly multiplexed to generate and send an excitation signal, and the scoreboard accesses the kernel register through a back door and automatically compares the kernel register with an expected value of the reference model to obtain a verification result; when the data sent to a bus by the SOC is verified, the excitation generator and the driver are closed, a driving program is loaded to the risc-v kernel, an IP module is driven by the on-chip bus to send the data, the monitoring module collects the sent data, and the scoreboard judges a final result. The system has the following beneficial effects that the verification time is greatly shortened while the test flexibility is ensured.

Description

technical field [0001] The invention relates to the technical field of chip verification, in particular to a UVM-based SOC verification system and method. Background technique [0002] With the development of large-scale integrated circuits, SOC system-on-chip integrates more and more IP modules, the complexity and integration of chips continue to increase, and the requirements for verification are getting higher and higher. Verification occupies 80% of the time in the entire chip design work. How to quickly and accurately build a verification platform, develop effective verification incentives, and find out design problems as soon as possible brings huge challenges to the verification work. Contents of the invention [0003] In order to solve the above problems, the present invention proposes a UVM-based SOC verification system and method. [0004] A UVM-based SOC verification system, including randomly generated test stimuli covering design specifications, a verificatio...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/22G06F11/263G06F30/398
CPCG06F11/2236G06F11/263G06F30/398Y02D10/00
Inventor 赵燕
Owner 杭州德旺信息技术有限公司
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