SOC verification system and method based on UVM

A verification system and system-on-chip technology, applied in the field of UVM-based SOC verification system, to achieve the effect of ensuring correctness, avoiding repeated development, and ensuring test flexibility
CN113297017AActive Publication Date: 2021-08-24杭州德旺信息技术有限公司
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
杭州德旺信息技术有限公司
Publication Date
2021-08-24

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Abstract

The invention relates to the technical field of chip verification, in particular to an SOC verification system and method based on UVM, and the system comprises a test excitation which covers design specifications and is randomly generated, a verification environment layer which is formed by combining a plurality of IP_ENVs, and a system-on-chip SOC based on a risc-v kernel. Each IP_ENV comprises a scoreboard, a kernel register, a reference model, an excitation generator, a driver and a monitoring module. When data sent by peripheral equipment to the SOC is verified, a verification environment is directly multiplexed to generate and send an excitation signal, and the scoreboard accesses the kernel register through a back door and automatically compares the kernel register with an expected value of the reference model to obtain a verification result; when the data sent to a bus by the SOC is verified, the excitation generator and the driver are closed, a driving program is loaded to the risc-v kernel, an IP module is driven by the on-chip bus to send the data, the monitoring module collects the sent data, and the scoreboard judges a final result. The system has the following beneficial effects that the verification time is greatly shortened while the test flexibility is ensured.
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Description

technical field

[0001] The invention relates to the technical field of chip verification, in particular to a UVM-based SOC verification system and method. Background technique

[0002] With the development of large-scale integrated circuits, SOC system-on-chip integrates more and more IP modules, the complexity and integration of chips continue to increase, and the requirements for verification are getting higher and higher. Verification occupies 80% of the time in the entire chip design work. How to quickly and accurately build a verification platform, develop effective verification incentives, and find out design problems as soon as possible brings huge challenges to the verification work. Contents of the invention

[0003] In order to solve the above problems, the present invention proposes a UVM-based SOC verification system and method.

[0004] A UVM-based SOC verification system, including randomly generated test stimuli covering design specifications, a verificatio...

Claims

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