System and method for hierarchical power verification

Abstract

A hierarchical power verification system and method creates abstract models of power behavior of modules that it successfully verifies. The abstract models simplify the module definition by omitting internal module details but provide sufficient information for power verification of higher level modules that incorporate this abstracted module. Design blocks are replaced with these abstract power models, resulting in reduced run-time and memory requirements. The power models can include power switches inside the block, related supplies of logic ports, supply power states, system power states, power management devices such as isolation logic and level shifters, feed-through and floating ports. The power model may be expressed either in UPF or as a combination of liberty model and UPF. After replacing modules with abstracted models the HPVS can quickly verify an entire SoC with a small memory footprint. When a user modifies a module, the HPVS need only verify the changed module and related modules at higher levels of module hierarchy.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims priority under 35 U.S.C. 119(e) from prior U.S. provisional application No. 62 / 189,453, filed Jul. 7, 2015.TECHNICAL FIELD[0002]This invention relates to the field of integrated circuits verification and in particular to verification of power subsystems. More particularly the invention relates to a system, method and computer program product for efficiently verifying the power subsystems of large system-on-a-chip designs.BACKGROUND ART[0003]Low power consumption in a SoC (System on Chip) is increasingly important. SoC designs incorporate many techniques to reduce power consumption. One technique is for the designer to use multiple voltage levels, since the voltage needs to be high only for high frequency modules of the SoC, and low voltage levels reduce power consumption. Modules of a SoC that have voltages powering them that are different from the voltages powering some other module to which they are connected are ...

AI Technical Summary

Benefits of technology

[0015]According to the power verification method, the system's processor prepares the abstract models for each circuit module to be verified by performing in any order one or more of: (1) capture interface supplies, (2) create domains, (3) identify related supplies, (4) establish power state tables, (5) model isolation logic, (6) model level shifters, (7) model feed-through floating ports, and (8) model power switches. Design

Problems solved by technology

As SoC designs continue to grow in terms of complexity and number of transistors, the verification time increases and the memory requirements of the ED

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