Automatic chip validation method based on parameterized IP test case set

Abstract

The invention discloses an automatic chip validation method based on a parameterized IP test case set. The automatic chip validation method is achieved by adding test stimulus of IP test cases to the traditional validation method. The automatic chip validation method includes the following steps: designing the test case set of each IP constituting a chip; setting the parameter of each IP constituting the chip; setting the corresponding test case set according to the parameter definition of each IP during design; testing each IP in the chip on the basis of the set test case set to verify the correctness of the design. The automatic chip validation method can be achieved simply, greatly reduces expenses for re-writing of the test cases for the same IP, and improves the IP-based chip validation efficiency.

Description

technical field [0001] The invention relates to the automatic verification technology of chips based on IP, and is especially suitable for the function verification of large-scale integrated circuits based on IP. Background technique [0002] With the advancement of integrated circuit technology, more and more transistors are integrated on a single chip, and the increase in the scale of integrated circuits makes design and verification very complicated. In order to improve the efficiency of chip design and reduce the time cost of design and verification , design and development based on highly mature IP has become a mainstream way of VLSI design. [0003] For this type of IP-based chip design, since different designs will have different usage methods for IP, different configuration parameters will be selected, and different test cases will be constructed for different chips according to the chip program during verification, resulting in Different designs will have different...

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Problems solved by technology

[0003] For this type of IP-based chip design, since different designs will have different usage methods for IP, different configuration parameters will be selected, and different test cases will be constructed for different chips according to the chip program during verification, resulting in Different designs will have different verification cases to ensure consistency with IP configuration parameters, so even if the same IP is used in different projects, it will bring a lot of test case writing time and verification time overhead

With the advancement of semiconductor technology, the complexity of the chip is further increased, and a large number of mature IP will be used on a single chip, which will increase the verification time. The traditional method of writing test cases is difficult to meet the requirements of a large number of IP applications. verification requirements

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