Cache consistency detection system and method

Abstract

The invention provides a cache consistency detection system and method. The system comprises a plurality of CPU core first-level cache mirror images, first-level cache row detection modules in one-to-one corresponding to the CPU core first-level cache mirror images, a second-level cache mirror image, a second-level cache row detection module corresponding to the second-level cache mirror image, abackfill request monitor, a replacement request monitor, a snoop request monitor and a comparator. The invention can dynamically cover the detection of all application scenes of the real system in real time, and improves the efficiency of cache consistency detection.

Description

technical field [0001] The invention relates to the technical field of CPU design, in particular to a cache consistency detection system and method. Background technique [0002] With the rapid development of semiconductor manufacturing technology, the main frequency of single-core processors has gradually reached the limit. In order to further improve the performance of the processor, it is necessary to integrate multiple processor cores into one chip to form a multi-core processor. Cache (cache) is located between the processor and the memory, and is used to match the access speed between the memory and the processor, so that the CPU in the multi-core processor has both the speed of the cache and the capacity of the main memory. [0003] In a multi-core processor, the gap between the access speed of the processor and the memory to the same memory unit becomes very obvious, so the multi-core processor design can alleviate this contradiction through a multi-level cache hiera...

AI Technical Summary

Problems solved by technology

[0007] Due to the limited types of memory access patterns of the manually written parallel consistency verification program in system-level verification, it cannot fully verify the consistency of the processor cache

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