Novel 8 digit RISC micro controller frame

Abstract

This invention discloses one new eight bit RISC micro controller frame, which is characterized by the following: the second degree four section streamline structure comprises order process device, data reading device, data computing device, data writing back device and clock generator. The technique achievements are ad following: making each clock non-crossing coupling to ensure the stable clock; each device relies on each other and to pre-process data to improve the structure to realize the high productivity.

Description

technical field [0001] The invention belongs to the field of semiconductor integrated circuit design, and in particular relates to a microcontroller (MCU) system framework. Background technique [0002] In recent years, the reduced instruction set (RISC) architecture of microcontrollers has gained widespread popularity. Although there are different opinions on what characteristics a RISC processor should have, various RISC architectures share the following characteristics: (1) most instructions are single-cycle instructions to facilitate pipelining of the structure; (2) independent and simple loading and store instructions are two-cycle instructions; (3) instruction decoding is usually hardwired rather than micro-decoding to speed up execution; (4) most instructions have a fixed format to simplify instruction encoding and decoding; (5) ) a smaller instruction set and a few addressing modes; (6) the data channel is pipelined to make the processing process highly parallel; (7...

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Problems solved by technology

[0003] These characteristics of RISC microcontrollers also bring some essential defects and deficiencies: (1) The instruction set cannot be expanded; (2) There are many pipeline segments and stages, which brings the complexity of data correlation criteria in pipeline segments , sometimes even affects the data throughput of the pipeline; (3) the data memory and the program memory are multiplexed, there is no special register file, or the special register file is not separated from the general register file, which affects the access speed of these registers and limits the (4) The design for testability (DFT) is not adopted, and the manufacturing and production quality of the product cannot be guaranteed in the application; (5) The biggest problem that has not yet been solved is: for the two-pole four-stage flow structure, each module They cannot back up each other, rely on each other, let alone preprocess and process the data, which seriously affects the anti-interference ability of the structure

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