GPDSP framework-oriented multi-kernel directory consistency apparatus

A consistency and directory technology, applied in the direction of instrumentation, electrical digital data processing, etc., can solve the problems of difficulty in realizing data consistency, and achieve the effects of wide application range, shortened design and verification cycle, and high flexibility

Active Publication Date: 2016-12-07
NAT UNIV OF DEFENSE TECH
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0006] In GPDSP, the on-chip memory and DMA background transfer mechanism in the cor

Method used

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  • GPDSP framework-oriented multi-kernel directory consistency apparatus
  • GPDSP framework-oriented multi-kernel directory consistency apparatus
  • GPDSP framework-oriented multi-kernel directory consistency apparatus

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Embodiment Construction

[0036] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0037] In a specific application example, the GPDSP architecture includes N cores; GetX request means GetS request or GetM request; Fwd-GetX request means Fwd-GetS request or Fwd-GetM request; PutX request means PutS request or PutM+data request; directory X The status indicates the directory S status or the directory M status; the directory Y status indicates the directory S status or the directory I status.

[0038] Such as figure 1 As shown, the multi-core directory consistency device for GPDSP architecture of the present invention includes:

[0039] Kernel, including DMA and Level 1 Data Cache (L1D); among them, DMA is used to transfer data between peripherals and kernel, and requires programmer configuration before starting. There are two parallel processing units, Normal Deal and Monitor Deal, in L1D. Among them, the Normal D...

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Abstract

The invention discloses a GPDSP (General-Purpose Digital Signal Processor) framework-oriented multi-kernel directory consistency apparatus. The apparatus comprises kernels, an on-chip last-level Cache, an off-chip memory DDR and an on-chip interconnection network. Each kernel comprises DMA and L1D, wherein L1D is a first-level data Cache; the DMA is used for finishing transfer of data between a peripheral and the kernel; the L1D comprises two parallel processing units of Normal Deal and Monitor Deal; the Normal Deal processing unit finishes processing of load and store instructions; and the Monitor Deal processing unit is used for making a response to a monitoring request arrived at any moment, and the processing process is not influenced by the Normal Deal processing unit. The on-chip last-level Cache is connected to the on-chip interconnection network in a distributed way. Data in the off-chip memory DDR is cached in the L1D and the on-chip last-level Cache. The on-chip interconnection network is used for receiving a network request, performing decoding processing first to obtain a destination node and a destination device after receiving the network request, and sending the request to a corresponding position. The apparatus has the advantages of simple principle, convenient operation, high flexibility, wide application range and the like.

Description

technical field [0001] The invention mainly relates to the field of processor micro-architecture design, in particular to a design suitable for multi-core storage paths of a General-Purpose Digital Signal Processor (GPDSP). Background technique [0002] As one of the troika (CPU, DSP and GPU) in the field of processors, DSP is widely used in embedded systems due to its advantages of high performance per power ratio, good programmability and low power consumption. Different from the CPU, DSP has the following characteristics: 1) Strong computing power, focusing on implementation calculations rather than control and transaction processing; 2) It has specialized hardware support for typical signal processing, such as multiplication and addition operations, circular addressing, etc.; 3 ) The common characteristics of embedded microprocessors, such as address and instruction path not more than 32 bits; imprecise interrupt; short-term offline debugging, long-term online resident r...

Claims

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Application Information

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IPC IPC(8): G06F13/30
CPCG06F13/30G06F2213/2806
Inventor 刘胜李昭然陈海燕许邦建鲁建壮陈俊杰孔宪停康子扬
Owner NAT UNIV OF DEFENSE TECH
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