Method for extracting clock tree based on comprehensive netlist in chip design and application

Abstract

The invention discloses a method for extracting a clock tree based on a comprehensive netlist in chip design and application, and relates to the technical field of integrated circuit design. The method comprises the following steps: in a logic synthesis step, obtaining logic synthesis netlist information of a chip top layer and a sub-module, and module information and clock constraint file information of chip segmentation; splicing a clock structure of the whole chip according to the obtained information, and obtaining a clock source from a clock constraint file; based on full-chip clock structure information, performing tracking backwards step by step from a clock source by adopting a recursive algorithm to form a full-chip clock tree network; in the tracking process, determining starting points and ending points of the top-layer clock tree and the sub-module clock tree according to the clock tree tracking path; and after the tracking is finished, classifying the clock structures of the top layer and the sub-modules to form a clock tree implementation guidance file. According to the method, the clock tree verification period is shortened, and the efficiency and correctness of clock tree implementation work are improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a method for extracting a clock tree in chip design. Background technique [0002] With the maturity of 5G and artificial intelligence technology, there are more and more requirements for chip functions in the development process, and the scale of chips is also getting larger and larger, but the expected chip design cycle is getting shorter and shorter. How to optimize chip design It is one of the current main research directions to improve the design efficiency and reduce the waste of design resources in the process of chip design. The main process of a typical chip design generally includes the following steps: specification formulation, architecture design, clock design, code writing, simulation verification, logic synthesis, formal verification, testability design, layout planning (or layout), clock tree Implementation (or Clock Tree Synthesis), Wiring Plan...

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Problems solved by technology

[0005] However, on the one hand, because clock tree design is in the early stage of chip design, and clock tree analysis and implementation are in the later stage of chip design, there are a lot of other design analysis work between the two in the chip design process. If clock tree analysis and implementation If there is a problem with the clock tree in the stage, it is often necessary to modify the previous design plan, resulting in a large amount of work between the two stages may be invalid, increasing the iteration time and prolonging the chip design cycle

On the other hand, the current clock implementation of large-scale chips is usually implemented in a bottom-up, sub-module independent implementation, and then the connectivity and correctness are verified through top-level splicing. This method relies on the constraint files of the sub-modules High reliability, if there is a problem with the clock tree in the submodule constraint file, the submodule itself is often unable to find the above problem, and the above problem can only be found when the top layer is spliced ​​later. Due to the delay in solving the above problem, the risk of iteration is increased

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